Non-volatile memory device and memory system including the same and program method thereof

A three dimensional non-volatile memory device, comprising:

• a memory cell array including a cell string, the cell string including a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate, wherein the memory cells comprise a first cell group and a second cell group stacked on the first cell group, and wherein a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate;
• an address decoder configured to a supply string selection line voltage to the string selection transistor, word line voltages to word lines connected to the memory cells, a ground selection line voltage to the ground selection transistor, and a common source line voltage to a common source line of the memory cell array;
• a page buffer circuit configured to output bit data from selected ones of the memory cells of the memory cell array;
• control logic;
• and
• a voltage generator configured to supply voltages to the address decoder in response to the control logic,
• wherein the memory device is configured to initialize a channel of a memory cell being selected of the first cell group of the cell string through the ground selection transistor, and then apply a program voltage to the memory cell of the pillar structure of the cell string.

A method of programming a three-dimensional (3D) nonvolatile memory device, including a memory cell array having a plurality of cell strings each connected to one of a plurality of bit lines, the cell strings each including a pillar structure comprising a ground selection transistor, a plurality of memory cells each connected to one of a plurality of word lines, and a string selection transistor stacked vertically over a substrate, wherein the memory cells of each cell string comprise a first cell group and a second cell group stacked on the first cell group, and wherein a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate, the method comprising:

• providing bit line voltages to the bit lines to select one of the bit lines;
• supplying string selection line voltages to string selection transistors of cell strings connected to the selected bit line to select one of the cell strings;
• and
• precharging the pillar structure of the selected cell string through the ground selection transistor of the selected cell string, and then applying word line voltages to the word lines connected to the memory cells of the cell string to program a selected memory cell.