Back to results
US 10,541,031 B2Granted
Single pulse SLC programming scheme
AssigneeSanDisk Technologies LLC
InventorsMohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
Life of this patent
Estimating the term…
Abstract
A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
Claims22
A circuit comprising:
- a memory array comprising a plurality of word lines and bit lines, each bit line coupled to a channel;
- a word line voltage supply circuit configured to supply a single program pulse to a selected word line to program a single page of data into a plurality of memory cells of a block;
- a word line zone decoder circuit configured to:
- identify a word line zone of the block in which the selected word line is disposed;
- and
- identify a set of channel voltages that correspond to the identified word line zone and to channels that intersect the identified word line zone;
- and
- a bit line voltage supply circuit configured to bias the channels with the channel voltages according to a plurality of bit line zones, the bit line zones extending from one end of the selected word line to the other end of the selected word line.
5 more elements
A circuit comprising:
- a row decoder configured to supply program pulses to word lines during program operations;
- and
- a program controller configured to:
- identify a word line address of a selected word line for programing a plurality of single-level memory cells with a single program voltage pulse;
- determine a word line zone identifier from among a plurality of word line zone identifiers associated with the word line address;
- and
- output a control signal to set drain-side voltages each to one of a plurality of selected drain-side levels based on the word line zone identifier and a position of the bit lines relative to the row decoder.
4 more elements
A system comprising:
- a block comprising a plurality of word lines;
- a plurality of memory cells three-dimensionally arranged in the block;
- a row decoder configured to:
- supply a first program pulse to a first word line to program a first group of single-level memory cells during a first program operation;
- and
- supply a second program pulse to a second word line to program a second group of single-level memory cells during a second program operation, the second word line positioned in a higher word line zone than the first word line;
- and
- a column decoder configured to:
- during supply of the first program voltage pulse, supply a first set of voltages at a first set of decreasing voltage levels based upon the word line zone of the first word line to a first set of selected channels of the block;
- and
- during supply of the second program voltage pulse, supply a second set of voltages at a second set of decreasing voltage levels based upon the word line zone of the second word line to a second set of selected channels of the block.
8 more elements
A method comprising:
- identifying, with a program controller, a selected word line coupled to a group of single-level memory cells for a program operation;
- identifying, with the program controller, a word line zone in which the selected word line is positioned;
- and
- supplying, with a bit line voltage supply circuit, a plurality of channel voltages at a set of decreasing levels to selected channels based on the word line zone and a plurality of bit line zones during the program operation.
1 more element
A circuit comprising:
- a means for supplying a single program pulse to a selected word line to program a single page of data into a plurality of memory cells of a block;
- a means for identifying a set of channel voltages that correspond to a word line zone of the block and to channels that intersect the word line zone;
- and
- a means for biasing channels with the set of channel voltages according to a plurality of bit line zones, the bit line zones extending from one end of the selected word line to the other end of the selected word line.
1 more element
Dependencies are inferred from the claim text.