Partial block memory operations

An apparatus comprising a block of memory cells, the block of memory cells comprising:

• strings of charge storage devices, each string comprising charge storage devices formed in a. plurality of tiers;
• multiple memory tile columns, wherein each of the multiple memory tile columns includes a number of the strings of charge storage devices wherein each of the strings is only within a single one of the multiple memory tile columns;
• global access lines shared by the strings, each global access line configured to be coupled to the charge storage devices within a selected one of the multiple memory tile columns through a sub-access line coupled to a respective tier of the plurality of tiers within the selected one of the multiple memory tile column, wherein the sub-access line is one of access lines coupled to the multiple memory tile columns;
• a separate sub-source coupled to each of the multiple memory tile columns, each sub-source coupled to a source select gate (SGS) of each string within respective ones of the multiple memory tile columns, each sub-source independently selectable from other sub-sources to select the strings of its respective memory tile column independently of other strings corresponding to other memory tile columns;
• sub-source select gate (sub-SGS) lines, each sub-SGS line coupled to the SGS of each string of respective memory tile column , each sub-SGS line independently selectable from other sub-SGS lines corresponding to other strings in other memory tile columns;
• and
• sub-drain select gate (sub-SGD) lines, each sub-SGD line coupled to a drain select gate (SGD) of each string of a respective memory tile column , wherein each sub-SGD line is independently selectable from other sub-SGD lines corresponding to other strings in other memory tile columns, wherein:
• the multiple memory tile columns include a first memory tile column coupled to a first sub-source, and a second multiple memory tile column coupled to a second sub-source;
• the sub-access lines include first sub-access lines and second access lines;
• charge storage devices in each tier of the plurality of tiers in the first memory tile column is coupled to one of the first sub-access lines;
• charge storage devices in each tier of the plurality of tiers in the second memory tile column is coupled to one of the second sub-access lines;
• and
• the first sub-access lines are electrically separated from the second access lines.