Switching block configuration bit comprising a non-volatile memory cell

A method for a system having a switching block routing array comprising a plurality of inputs, a plurality of outputs and a plurality of configuration bits coupled to the plurality of inputs and the plurality of outputs, wherein each of the plurality of configuration bits comprise a first two-terminal volatile switch coupled to a first non-volatile switch, the method comprising:

• applying with a programming circuit, a first programming signal to a first configuration bit from the plurality of configuration bits to thereby accumulate a first positive charge on a first control gate of a first non-volatile switch of the first configuration bit, wherein a first two-terminal volatile switch is coupled to the first control gate of the first non-volatile switch, wherein a first input node of the first non-volatile switch is coupled to a first input from the plurality of inputs, and wherein a first output node of the first non-volatile switch is coupled to a first output from the plurality of outputs;
• removing with the programming circuit, the first programming signal from the first configuration bit to thereby maintain at least a second positive charge on the first control gate, wherein the first non-volatile switch is characterized by a high conductive state in response to the second positive charge being maintained on the first control gate;
• thereafter coupling with the first non-volatile switch, the first input node to the first output node to thereby couple the first input of the switching block routing array to the first output of the switching block routing array in response to the first non-volatile switch being in the high conductive state;
• receiving with the first input of the switching block routing array, a first signal input;
• and
• providing with the first output of the switching block routing array, the first signal input in response to the first non-volatile switch being in the high conductivity state.