Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines

A method in a memory system comprising a memory cell including at least one storage circuit and at least one read SQUID, the method comprising performing a read operation and a write operation:

• the read operation comprising:
• (1) applying bit-line current, via a read bit-line not including any Josephson transmission line (JTL) elements, to the at least one read SQUID;
• (2) applying word-line current, via a read word-line not including any JTL elements, to the at least one read SQUID;
• and (3) using the at least one read SQUID reading a logic state of the memory cell based on data maintained in the storage circuit, wherein the at least one storage circuit comprises a differential flip-flop (DFF), wherein the DFF is configured to provide a first current to the at least one read SQUID when the memory cell is in a logic one state and provide a second current to the at least one read SQUID when the memory cell is in a logic zero state, wherein an amount of the first current is higher than an amount of the second current and
• the write operation comprising:
• applying a word-line current to the memory cell via a write-word line comprising a JTL element clocked by a clock, and wherein signals on neither the read bit-line nor the read word-line are phase-aligned with respect to the at least one JTL element being clocked by the clock.

A memory system comprising:

• an array of memory cells arranged in rows and columns;
• a set of read word-lines coupled to a plurality of memory cells in the array of the memory cells;
• a set of read bit-lines coupled to the plurality of memory cells in the array of the memory cells;
• and
• a set of write word-lines coupled to the first plurality of memory cells in the array of memory cells, wherein each of the set of the write word-lines comprises a line including at least one Josephson transmission line (JTL) element being clocked by a clock, and wherein each of the plurality of the memory cells comprises:
• at least one differential flip-flop (DFF) and at least one read superconducting quantum interference device (SQUID), wherein a read bit line corresponding to the set of read bit lines is coupled to the at least one read SQUID and a read word-line corresponding to the set of the read word-lines is coupled to the at least one read SQUID, wherein neither the read bit-line nor the read word-line is coupled to the at least one read SQUID via a JTL, wherein the at least one read SQUID is configured to read the data stored in the at least one DFF in response to an application of word-line current via one of the set of read word-lines, wherein the DFF is configured to provide a first current to the at least one read SQUID when the memory cell is in a logic one state and provide a second current to the at least one read SQUID when the memory cell is in a logic zero state, wherein an amount of the first current is higher than an amount of the second current, wherein signals on neither the read bit line nor the read word-line are phase-aligned with respect to the at least one JTL element being clocked by the clock.