Controller architecture for reducing on-die capacitance
AssigneeSeagate Technology LLC
InventorNitin Kumar Chhabra
Life of this patent
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Abstract
The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
Claims12
A dual-channel DDR interface, comprising:
- a lower DQ Strobe (LDQS) IO port configured to generate a LDQS signal that is substantially 0.125 of a period of a clock signal ahead of a rising edge of the clock signal;
- an upper DQS (UDQS) IO port configured to generate an UDQS signal that is substantially 0.125 of the period of the clock signal behind the rising edge of the clock signal;
- a first plurality of data ports, wherein each of the first plurality of data ports is configured to generate a data signal that is substantially 0.25 of the period of the clock signal away from the LDQS signal;
- and
- a second plurality of data ports, wherein each of the second plurality of data ports is configured to generate a data signal that is substantially 0.25 of the period of the clock signal away from the UDQS signal.
A system comprising:
- a dual-channel DDR interface, including:
- a plurality of DQ Strobe (DQS) IO ports including a lower DQS IO port and an upper DQS IO port, the lower DQS IO port configured to generate a LDQS signal that is substantially 0.125 of the period of the clock signal ahead of the rising edge of the clock signal and the upper DQS IO port configured to generate an UDQS signal that is substantially 0.125 of the period of the clock signal behind the rising edge of the clock signal;
- a first plurality of data ports, wherein each of the first plurality of data ports is configured to generate a data signal that is substantially 0.125 of the period of the clock signal away from the LDQS signal;
- and
- a second plurality of data ports, wherein each of the second plurality of data ports is configured to generate a data signal that is substantially 0.125 of the clock signal away from the UDQS signal.
A method of operating a dual channel DDR interface comprising:
- generating a LDQS signal that is substantially 0.125 of a period of a clock signal ahead of a rising edge of the clock signal;
- generating a UDQS signal that is substantially 0.125 of the period of the clock signal behind the rising edge of the clock signal;
- generating a first data signal that is substantially 0.25 of the period of the clock signal away from the LDQS signal;
- and
- generating a second data signal that is substantially 0.25 of the period of the clock signal away from the UDQS signal.
Dependencies are inferred from the claim text.