DDR memory bus with a reduced data strobe signal preamble timespan
AssigneeIntel Corporation
InventorsJames A. McCall, Christopher P. Mozak, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang
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Abstract
A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
Claims20
A semiconductor chip, comprising:
- a) memory controller circuitry to interface to a dual data rate (DDR) memory channel, said memory controller circuitry comprising first configurable on-die termination (ODT) circuitry to terminate a data strobe signal trace of said DDR memory channel, said memory controller circuitry comprising second configurable ODT circuitry to terminate a data signal trace of said DDR memory channel's data bus;
- b) configuration register space, said configuration register space comprising a first region to enter first ODT values for said first configurable ODT circuitry, said configuration register space comprising a second region to enter second ODT values for said second configurable ODT circuitry, wherein said first configuration register space is to be programmed with first ODT values that do not change if consecutive write operations of said DDR memory bus write to a different rank of a same memory module.
A memory chip, comprising:
- circuitry to interface to a dual data rate (DDR) memory channel, said circuitry comprising first configurable ODT circuitry to terminate a data strobe signal trace of said DDR memory channel, said circuitry comprising second configurable ODT circuitry to terminate a data signal trace of said DDR memory channel's data bus, said memory controller comprising configuration register space, said configuration register space comprising a first region to enter first ODT values for said first configurable ODT circuitry, said configuration register space comprising a second region to enter second ODT values for said second configurable ODT circuitry, wherein said first configuration register space is to be programmed with first ODT values that do not change if consecutive read operations of said DDR memory bus read from a different memory module.
A machine readable medium containing program code that when processed by semiconductor chip circuitry to execute program code causes a method to be performed, said method comprising:
- configuring first register space to establish ODT values of a data strobe signal trace of a dual data rate (DDR) memory channel;
- configuring second register space to establish ODT values of a data signal trace of said DDR memory channel's data bus, wherein, said ODT values for said data strobe signal trace are different than said ODT values for said data signal trace, and wherein, said ODT values for said data strobe signal trace do not change when consecutive write operations of said DDR bus write to different ranks of a same DIMM;
- programming said first configuration register space with first ODT values that do not change if consecutive read operations of said DDR memory bus read from a different memory module.
A computing system, comprising:
- a plurality of general purpose central processing unit (CPU) processing cores;
- a memory controller coupled to the plurality of general purpose processing cores;
- a main memory coupled to the memory controller with a DDR data bus, the main memory comprising a DIMM, the DIMM comprising:
- a) interface circuitry to interface to a dual data rate (DDR) memory channel, said interface circuitry comprising first configurable on-die termination (ODT) circuitry to terminate a data strobe signal trace of said DDR memory channel, said interface circuitry comprising second configurable ODT circuitry to terminate a data signal trace of said DDR memory channel's data bus;
- b) configuration register space, said configuration register space comprising a first region to enter first ODT values for said first configurable ODT circuitry, said configuration register space comprising a second region to enter second ODT values for said second configurable ODT circuitry, wherein said first configuration register space is to be programmed with first ODT values that do not change if consecutive write operations of said DDR memory bus write to a different rank of a same memory module.
Dependencies are inferred from the claim text.