Dual mode memory array security apparatus, systems and methods
AssigneeTexas Instruments Incorporated
InventorsChiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy
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AssigneeTexas Instruments Incorporated
InventorsChiraag Juvekar, Joyce Kwong, Clive Bittlestone, Srinath Ramaswamy
Estimating the term…
Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.
A system state verification apparatus, comprising:
A method of manufacturing a dual mode double cell (2T/2C) ferroelectric random access memory (FRAM) array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, the FRAM array imprinted with a physically unclonable function (“PUF”) pattern, comprising:
Dependencies are inferred from the claim text.