Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the same

A memory device, comprising:

• a memory controller;
• and
• a plurality of memory cells;
• wherein each of said plurality of memory cells comprises:
• a transistor;
• a magnetoresistive tunnel junction (MTJ) element;
• a tunneling magnetoresistance enhancement element (TMRE) coupled in series with the MTJ element;
• and
• the transistor is coupled in series with at least one of the MTJ element and the TMRE;
• and
• wherein:
• each MTJ element in said plurality of memory cells exhibits a transition between a first resistance state and a second resistance state in response to a voltage that is greater than or equal to a first switching voltage, VTH1;
• each TMRE in said plurality of memory cells exhibits a transition between a default resistance state and a switched resistance state in response to a voltage that is greater than or equal to a second switching voltage, VTH2;
• the first and second resistance states are a first low resistance state and a first high resistance state, respectively;
• the default and switched states are a second high resistance and a second low resistance state, respectively;
• and
• each memory cell of said plurality of memory cells is configured such that when an MTJ element thereof is in its first resistance state, the TMRE thereof is in its switched state, and when the MTJ element thereof is in its second resistance state, the TMRE thereof is in its default state.