Electronic device
AssigneeSK hynix Inc.
InventorsSeok-Man Hong, Tae-Hoon Kim
Life of this patent
Estimating the term…
Abstract
An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell; a first line coupled to a first end of the memory cell; a first coupling circuit to selectively couple a high voltage terminal to the first line in response to a first selection signal; a second line coupled to a second end of the memory cell; a second coupling circuit to selectively couple a first low voltage terminal to the second line in response to a second selection signal; and a first charge storing circuit selectively coupled to the first line in response to an enable signal, the enable signal corresponding to a predetermined operation mode when the memory cell is turned on.
Claims20
An electronic device including a semiconductor memory, wherein the semiconductor memory includes:
- a memory cell;
- a first line coupled to a first end of the memory cell;
- a first coupling circuit to selectively couple a high voltage terminal to the first line in response to a first selection signal;
- a second line coupled to a second end of the memory cell;
- a second coupling circuit to selectively couple a first low voltage terminal to the second line in response to a second selection signal;
- and
- a first charge storing circuit to store charges and supply the stored charges to the first line in response to an enable signal, the enable signal corresponding to a predetermined operation mode when the memory cell is turned on.
An electronic device including a semiconductor memory, wherein the semiconductor memory includes:
- a global bit line;
- a plurality of local bit lines;
- a global word line;
- a plurality of local word lines;
- a write circuit coupled between a high voltage terminal and an output terminal, the write circuit being outputting an operation current corresponding to any one of a plurality of operation modes to the output terminal based on a plurality of enable signals, the plurality of enable signals corresponding to the plurality of operation modes;
- a first global coupling circuit to selectively couple the output terminal to the global bit line in response to a first global selection signal;
- a first local coupling circuit to selectively couple one bit line selected from the local bit lines to the global bit line based on a plurality of first local selection signals;
- a plurality of memory cells disposed in respective intersection regions between the local bit lines and the local word lines and coupled between the local bit lines and the local word lines, each of the memory cells having a resistance state corresponding to the operation current;
- a second local coupling circuit to selectively couple one word line selected from the local word lines to the global word line based on a plurality of second local selection signals;
- a second global coupling circuit to selectively couple the global word line to a low voltage terminal in response to a second global selection signal;
- a control circuit to generate a control enable signal based on two or more enable signals selected from the plurality of enable signals;
- and
- a first charge storing circuit selectively coupled to the global bit line in response to the control enable signal when a memory cell selected from the memory cells is turned on.
Dependencies are inferred from the claim text.