Shift register, method for driving same, gate driving circuit

A shift register, comprising:

• a pull-up module;
• a pull-down module;
• and
• a holding module,
• wherein,
• the pull-up module is connected to the holding module and the pull-down module, an electrical connection point of the pull-up module and the pull-down module constituting an output signal terminal, and configured to pull up a signal outputted at the output signal terminal in response to a first clock signal;
• the pull-down module is connected to the holding module and configured to pull down the signal outputted at the output signal terminal in response to a second clock signal;
• and
• the holding module is configured to hold a signal outputted from the pull-up module and the pull-down module at a fixed level;
• the pull-down module comprises a first transistor, a second transistor and a first capacitor,
• wherein:
• the first transistor has its gate connected to the first clock signal, its first electrode connected to a turn-on voltage signal and its second electrode connected to a gate of the second transistor,
• the second transistor has its gate further connected to a first terminal of the first capacitor, its first electrode connected to a second terminal of the first capacitor and to the pull-up module for constituting the out signal terminal, and its second electrode connected to the second clock signal;
• the pull-up module comprises a third transistor and a fourth transistor, wherein:
• the fourth transistor has its gate connected to the first clock signal, its first electrode connected to a low level signal and its second electrode connected to a gate of the third transistor, and
• the third transistor has its first electrode connected to a high level signal and its second electrode connected to the first electrode of the second transistor to constitute the output signal terminal;
• wherein the holding module comprises a fifth transistor and a sixth transistor,
• the fifth transistor has its gate connected to the second clock signal, its first electrode connected to the gate of the third transistor, and its second electrode connected to a second electrode of the sixth transistor, and the sixth transistor has its gate receiving the first clock signal and connected to its first electrode.