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US 10,540,742 B2Granted
Image warping in an image processor
AssigneeApple Inc.
InventorChristopher L. Mills
Life of this patent
Estimating the term…
Abstract
A device that includes integrated circuit includes a tiler circuit, a grid generator, and a warper circuit. The tiler circuit divides the distorted input image data into a plurality of image tiles and stores the image tiles into a memory device. Each image tile is an M×N array of pixel samples where M and N are greater than 1. The grid generator produces a mesh grid that describes a mapping of first pixel locations of the distorted image data to second pixel locations of the corrected image data. The warper circuit reads one or more of the image tiles from the memory device based on the mesh grid and interpolates a warped output image from the image tiles read from memory.
Claims16
A circuit, comprising:
- a tiling circuit configured to divide an input image into a plurality of image tiles, and to store the image tiles into memory;
- a grid generator configured to generate a mesh grid that represents a mapping of first pixel locations of the input image to second pixel locations of an output image;
- and
- a warper circuit configured to read two or more of the image tiles from the memory as defined by the mesh grid and to warp the input image into the output image from the two or more image tiles read from the memory, the warper circuit comprising:
- a first grid interpolator configured to generate interpolated pixel locations along a direction from the mesh grid at a first time for a memory access circuit to pre-fetch at least the two or more of the image tiles at the first interpolated pixel locations from the memory and store the pre-fetched two or more image tiles in an image buffer, the interpolated pixel locations differing based on the mesh grid;
- and
- a second grid interpolator separate from the first grid interpolator, the second grid interpolator configured to generate the same interpolated pixel locations along the direction from the mesh grid at a second time subsequent to the first time for passing the pre-fetched two or more images in the image buffer through a filter to generate filtered pixels of the output image.
4 more elements
A method, comprising:
- dividing an input image into a plurality of image tiles by a tiling circuit of the image processing circuit;
- storing the image tiles into memory by the tiling circuit;
- generating a mesh grid that represents a mapping of first pixel locations of the input image to second pixel locations of an output image;
- generating, by a first grid interpolator of a warper circuit, interpolated pixel locations along a direction from the mesh grid at a first time for a memory access circuit to pre-fetch at least two or more of the image tiles at the interpolated pixel locations from the memory responsive to generating the interpolated pixel locations at the first time, the interpolated pixel locations differing based on the mesh grid;
- storing the pre-fetched two or more image tiles in an image buffer of the warper circuit;
- generating, by a second grid interpolator of the warper circuit separate from the first grid interpolator, the same interpolated pixel locations along the direction from the mesh grid at a second time subsequent to the first time;
- and
- passing the pre-fetched two or more images in the image buffer through a filter to generate filtered pixels of the output image.
5 more elements
A device, comprising:
- a memory;
- and
- an integrated circuit comprising:
- a tiling circuit configured to divide an input image into a plurality of image tiles, and to store the image tiles into memory;
- a grid generator configured to generate a mesh grid that represents a mapping of first pixel locations of the input image to second pixel locations of an output image;
- and
- a warper circuit configured to read two or more of the image tiles from the memory as defined by the mesh grid and to warp the input image into the output image from the two or more image tiles read from the memory, the warper circuit comprising:
- a first grid interpolator configured to generate interpolated pixel locations along a direction from the mesh grid at a first time for a memory access circuit to pre-fetch at least the two or more of the image tiles at the first interpolated pixel locations from the memory and store the pre-fetched two or more image tiles in an image buffer, the interpolated pixel locations differing based on the mesh grid;
- and
- a second grid interpolator separate from the first grid interpolator, the second grid interpolator configured to generate the same interpolated pixel locations along the direction from the mesh grid at a second time subsequent to the first time for passing the pre-fetched two or more images in the image buffer through a filter to generate filtered pixels of the output image.
7 more elements
Dependencies are inferred from the claim text.