Processing unit performance projection using dynamic hardware behaviors

A computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:

• receiving machine code configured for a first architecture of a first processing unit;
• simulating execution of the machine code on the first processing unit;
• monitoring the simulated execution to determine a plurality of performance characteristics;
• determining a plurality of dynamic hardware behaviors by applying a clustering algorithm to the plurality of performance characteristics, wherein determining a first one of the plurality of dynamic hardware behaviors comprises clustering two or more windows of time during the execution based on corresponding performance characteristics of the first processing unit during the two or more windows of time;
• generating a representative set of instructions to collectively represent the two or more windows of time;
• and
• generating an equivalent accelerator portion of machine code configured for a second architecture of a second processing unit, by translating the representative set of instructions to an equivalent set of instructions configured for the second architecture, wherein the equivalent set of instructions approximates the representative set of instructions but does not match a functionality of at least one of the two or more windows of time.

A system comprising:

• a processor;
• and
• a computer memory storing a program, which, when executed on the processor, performs an operation comprising:
• receiving computer program code to be executed on a first processing unit;
• monitoring an execution of the computer program code on the first processing unit to determine a plurality of performance characteristics;
• determining a plurality of dynamic hardware behaviors by applying a clustering algorithm to the plurality of performance characteristics, wherein determining a first one of the plurality of dynamic hardware behaviors comprises clustering two or more windows of time during the execution based on corresponding performance characteristics of the first processing unit during the two or more windows of time;
• generating a representative set of instructions to collectively represent the two or more windows of time;
• generating an equivalent accelerator portion of computer program code by translating the representative set of instructions to an equivalent set of instructions to be executed on a second processing unit, wherein the equivalent set of instructions approximates the representative set of instructions but does not match a functionality of at least one of the two or more windows of time;
• and
• determining, for the first one of the plurality of dynamic hardware behaviors, an estimated measure of performance for executing the equivalent accelerator portion on the second processing unit.