US 10,540,736 B2Granted

Display sub-system sharing for heterogeneous systems

AssigneeTexas Instruments Incorporated

InventorsSunita Nadampalli, Anish Reghunath, Brian Okchon Chae, Jonathan Elliot Bergsagel, Gregory Raymond Shurtz

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Abstract

An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.

Claims17

Dependent claims

An integrated circuit comprising:

a first control port;
a second control port;
an output port adapted to be coupled to a display device;
a first image processing resources, the first image processing resources comprising:
a first set of image processing pipelines configured to operate in parallel;
and
a first overlay logic coupled to the first set of image processing pipelines and the output port, the first overlay logic is configured to:
receive a first set of respective image data from each of the first set of image processing pipelines;
and
output an overlay of the first set of respective image data to the output port;
a second image processing resource, the second image processing resource comprising:
a second set of image processing pipelines configured to operate in parallel;
and
a second overlay logic coupled to the second set of image processing pipelines and the output port, the second overlay logic is configured to:
receive a second set of respective image data from each of the second set of image processing pipelines;
and
output an overlay of the second set of respective image data to the output port;
a first interrupt request (IRQ) aggregation logic configured to:
receive a first IRQ signal from a first image processing pipeline in the first set of image processing pipelines and a second IRQ signal from a second image processing pipeline in the first set of image processing pipelines;
mask the first IRQ signal;
aggregate the masked first IRQ signal and the second IRQ signal into an aggregated first set of IRQ signals;
and
communicate the aggregated first set of IRQ signals to the first control port;
and
a second IRQ aggregation logic configured to:
receive a third IRQ signal from a first image processing pipeline in the second set of image processing pipelines and a fourth IRQ signal from a second image processing pipeline in the first set of image processing pipelines;
aggregate the third and fourth IRQ signals into an aggregated second set of IRQ signals;
and
communicate the masked aggregated second set of IRQ signals to the second control port.

26 more elements

A method comprising:

allocating a first portion of image processing resources and a first set of interrupt request aggregation logic to a first processor, wherein the first portion of image processing resources comprises a first set of image processing pipelines configured to operate in parallel;
allocating a second portion of image processing resources and a second set of interrupt request aggregation logic to a second processor, wherein the second portion of image processing resources comprises a second set of image processing pipelines configured to operate in parallel;
receiving, by the first portion of image processing resources, first image data from the first processor;
receiving, by the second portion of image processing resources, second image data from the second processor;
overlaying, by the first portion of image processing resources, first image data to produce first image output data;
and
overlaying, by the second portion of image processing resources, second image data to produce second image output data;
receiving, by the first set of interrupt request aggregation logic, a first interrupt request signal from a first image processing pipeline in the first set of image processing pipelines and a second interrupt request signal from a second image processing pipeline in the first set of image processing pipelines;
masking, by the first set of interrupt request aggregation logic, the first interrupt request signal;
aggregating, by the first set of interrupt request aggregation logic, the masked first interrupt request signal and the second interrupt request signal into an aggregated first set of interrupt request signals;
and
communicating, by the first set of interrupt request aggregation logic, the aggregated first set of interrupt request signals to the first processor;
receiving, by the second set of interrupt request aggregation logic, a third interrupt request signal from a first image processing pipeline in the second set of image processing pipelines and a fourth interrupt request signal from a second image processing pipeline in the second set of image processing pipelines;
aggregating, by the second set of interrupt request aggregation logic, the third and fourth interrupt request signals into an aggregated second set of interrupt request signals;
and
communicating, by the second set of interrupt request aggregation logic, the masked aggregated second set of interrupt request signals to the second processor.

13 more elements

A method comprising:

allocating a first portion of image processing resources and a first set of interrupt request aggregation logic to a first processor;
allocating a second portion of image processing resources and a second set of interrupt request aggregation logic to a second processor;
receiving, by the first portion of image processing resources, first image data from the first processor;
receiving, by the second portion of image processing resources, second image data from the second processor;
receiving, by the first set of interrupt request aggregation logic, a first interrupt request signal from a first image processing pipeline in the first set of image processing pipelines and a second interrupt request signal from a second image processing pipeline in the first set of image processing pipelines;
masking, by the first set of interrupt request aggregation logic, the first interrupt request signal;
aggregating, by the first set of interrupt request aggregation logic, the masked first interrupt request signal and the second interrupt request signal into an aggregated first set of interrupt request signals;
and
communicating, by the first set of interrupt request aggregation logic, the aggregated first set of interrupt request signals to the first processor;
receiving, by the second set of interrupt request aggregation logic, a third interrupt request signal from a first image processing pipeline in the second set of image processing pipelines and a fourth interrupt request signal from a second image processing pipeline in the second set of image processing pipelines;
aggregating, by the second set of interrupt request aggregation logic, the third and fourth interrupt request signals into an aggregated second set of interrupt request signals;
and
communicating, by the second set of interrupt request aggregation logic, the masked aggregated second set of interrupt request signals to the second processor;
setting a security mode for the first portion of the image processing resources to secure mode while setting a security mode for the second portion of the image processing resources to unsecure mode;
prohibiting movement of image data from the first image processing resource in secure mode to the first image processing resource in unsecure mode;
establishing a plurality of firewalls with selected attributes associated with the first portion of the image processing resources, such that access to the first portion of the image processing resources is restricted to a requester with the selected attributes;
overlaying, by the first portion of image processing resources, first image data to produce first image output data;
overlaying, by the second portion of image processing resources, second image data to produce second image output data.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/668,453Filed 3 Aug 2017
Published: US 2019/0043153 A17 Feb 2019
Granted: 21 Jan 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06T 1/20
General purpose image data processing: processor architectures; Processor configuration, e.g. pipelining
G06F 3/0641
Management of blocks: de-duplication techniques
G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
G06F 9/544
Interprogram communication: buffers; Shared memory; Pipes