Chip temperature computation method and chip temperature computation device
AssigneeIndustrial Technology Research Institute
InventorsHeng-Chieh Chien, Sheng-Tsai Wu, Ming-Ji Dai, Chih-Ming Shen
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Abstract
A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.
Claims15
A chip temperature computation method for computing a temperature of a chip in a package structure, wherein the package structure comprises the chip, at least one upper layer of the chip, and a plurality of lower layers of the chip, the chip temperature computation method comprises:
- computing an upper layer thermal resistance corresponding to the at least one upper layer and a lower layer thermal resistance corresponding to the plurality of lower layers;
- and
- computing a total thermal resistance of the chip based on the upper layer thermal resistance and the lower layer thermal resistance, and computing a temperature of the chip based on the total thermal resistance,
- wherein the computing the lower layer thermal resistance comprises:
- building a thermal resistance performance database and an equivalent material parameter of each layer of the plurality of lower layers;
- obtaining a boundary condition of an Nth layer of the plurality of lower layers;
- and
- obtaining a thermal resistance of the Nth layer based on the boundary condition and the equivalent material parameter of the Nth layer and the thermal resistance performance database of the Nth layer, and converting the thermal resistance of the Nth layer into a boundary condition of an N+1th layer of the plurality of lower layers, wherein a distance between the Nth layer and the chip is greater than a distance between the N+1th layer and the chip.
A chip temperature computation device for computing a temperature of a chip in a package structure, wherein the package structure comprises the chip, at least one upper layer of the chip, and a plurality of lower layers of the chip, the chip temperature computation device comprises:
- a processor;
- and
- a memory coupled to the processor, wherein the processor is configured to:
- obtain a lower layer thermal resistance corresponding to the plurality of lower layers based on a boundary condition, a thermal resistance performance database, and an equivalent material parameter of each layer of the plurality of lower layers;
- obtain an upper layer thermal resistance corresponding to the at least one upper layer based on a boundary condition, a thermal resistance database, and an equivalent material parameter of the at least one upper layer;
- and
- compute a temperature of the chip based on the lower layer thermal resistance and the upper layer thermal resistance,
- wherein a thermal resistance of an Nth layer of the plurality of lower layers is associated with the boundary condition of an N+1th layer of the plurality of lower layers, and a distance between the Nth layer and the chip is greater than a distance between the N+1th layer and the chip.
Dependencies are inferred from the claim text.