Stacked chip layout and method of making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYing-Yu Hsu
Life of this patent
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Abstract
A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.
Claims20
A method of making a stacked chip layout, the method comprising:
- placing a plurality of active circuit blocks over a central processing chip, wherein the central processing chip has a first area, and each active circuit block of the plurality of active circuit blocks has an area less than the first area;
- and
- forming a plurality of routing regions over the central processing chip;
- wherein each routing region corresponds to an active circuit block of the plurality of active circuit blocks, each routing region is outside of the corresponding active circuit block and contacts a sidewall of the corresponding active circuit block, and at least one routing region of the plurality of routing regions overlaps with at least another routing region of the plurality of routing regions.
A method of making a stacked chip layout, the method comprising:
- depositing a first dielectric layer over a central processing chip;
- stacking a first active circuit block over the first dielectric layer;
- depositing a second dielectric layer over the first active circuit block;
- stacking a second active circuit block over the second dielectric layer, wherein the second active circuit block overlaps the first active circuit block in a partial overlap area, the second active circuit block exposes a portion of the first active circuit block, and the second active circuit block extends beyond at least one edge of the first active circuit block in a plan view;
- depositing a third dielectric layer over the second dielectric layer, wherein the third dielectric layer is a same distance from the central processing chip as the second active circuit block;
- and
- routing a local conductive element through the third dielectric layer and the second dielectric layer to electrically connect the first active circuit block to the second active circuit block.
A method of making a stacked chip layout, the method comprising:
- stacking a plurality of circuit block layers over a central processing chip, wherein stacking each of the plurality of circuit block layers comprises:
- stacking an active circuit block, and
- depositing a dielectric material on a same level as the active circuit block,
- wherein the active circuit block of each of the plurality of circuit block layers includes a first portion overlapping the active circuit block of every other circuit block layer of the plurality of circuit block layers, and a second portion exposed by the active circuit block of every other circuit block layer of the plurality of circuit block layers;
- and
- routing a global conductive element electrically connecting the central processing chip to the active circuit block of each of the plurality of circuit block layers, wherein the global conductive element is routed through the first portion of the active circuit block of each of the plurality of circuit block layers.
Dependencies are inferred from the claim text.