Generating a power grid for an integrated circuit

A method for implementing a power grid for a portion of an integrated circuit, the power grid comprising a plurality of wires and vias that electrically connect to power pins and ground pins of components in the integrated circuit, the method comprising:

• automatically generating, by a computer, commands for creating hardware descriptions of the wires and vias of the power grid based on a high level description, wherein the high level description includes a core grid and one or more sub grids that refer to the core grid;
• receiving a specification for incrementally repairing a specific portion of the power grid;
• and
• automatically re-generating commands for creating hardware descriptions of the wires and vias of only the specific portion of the power grid;
• and
• providing the automatically generated and re-generated commands to a power grid router for creating shapes corresponding to the wires and vias of the power grid for use in physically implementing the integrated circuit,
• wherein the automatically generated and re-generated commands are provided in a language that can be executed by the power grid router, and
• wherein the high level description further includes a generic net name, and
• wherein automatically generating includes mapping the generic net name to a specific power net for a sub-chip in the integrated circuit, and
• wherein one or both of the core grid and the sub grid comprises a layer object having one or more stripe objects, and
• wherein certain of the one or more stripe objects are specified as corresponding to the generic net name.

A system for implementing a power grid for a portion of an integrated circuit, the power grid comprising a plurality of wires and vias that electrically connect to power pins and ground pins of components in the integrated circuit, the system comprising:

• a storage that stores hardware descriptions of components in the portion of the integrated circuit;
• and
• a power grid compiler that is adapted to automatically generate commands for creating hardware descriptions of the wires and vias of the power grid based on a high level description of the power grid and the stored hardware descriptions of the components in the portion of the integrated circuit, the high level description including a core grid and one or more sub grids that refer to the core grid, wherein the power grid compiler is further adapted to provide the automatically generated commands to a power grid router for creating shapes corresponding to the wires and vias of the power grid for use in physically implementing the integrated circuit, and wherein the automatically generated commands are provided in a language that can be executed by the power grid router, and
• wherein the high level description further includes a generic net name, and
• wherein automatically generating includes mapping the generic net name to a specific power net for a sub-chip in the integrated circuit, and
• wherein one or both of the core grid and the sub grid comprises a layer object having one or more stripe objects, and
• wherein certain of the one or more stripe objects are specified as corresponding to the generic net name.