Leverage cycle stealing within optimization flows

A method of implementing timing adjustments in an integrated circuit, the method comprising:

• calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time of the latch, wherein the latch comprises at least one of the following:
• an unbalanced input timing slack and output timing slack, the output timing slack above a target threshold, or a cycle boundary occurring earlier than an end of an active clock interval;
• calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch;
• performing cycle stealing to improve the output timing slack by modifying the input required arrival time of the latch and the output arrival time;
• reducing the output timing slack by a pessimism amount, wherein the pessimism amount is based on at least one of the following:
• the input timing slack, estimating a maximum possible slack improvement, and calculating a difference between a current cycle boundary time and a time which corresponds with an end of an active clock interval;
• performing optimization by making design modifications in the integrated circuit to improve the input timing slack and the output timing slack until a desired slack goal is achieved, wherein performing optimization comprises at least one of the following:
• modifying a physical size of a logic device in the integrated circuit, changing a wire size in the integrated circuit and swapping design equivalents, wherein the desired slack goal comprises the output timing slack equal to zero;
• increasing the output timing slack by the pessimism amount;
• performing final power recovery, wherein performing final power recovery comprises:
• removing unnecessary output timing slack improvement, and removing unnecessary input timing slack improvement;
• and
• generating a final integrated circuit based on the final power recovery and creating a semiconductor chip based on the final integrated circuit.