Critical path aware voltage drop analysis of an integrated circuit

A system for circuit design analysis, comprising one or more processors, the one or more processors configured to:

• determine a number of cell instances with largest individual power consumption values in an integrated circuit design;
• determine, from static timing analysis on the integrated circuit design, a first number of circuit timing paths of the integrated circuit design with largest timing violations, the integrated circuit design having a plurality of circuit timing paths defined by the plurality of cell instances;
• determine, from the static timing analysis on the integrated circuit design, a second number of circuit timing paths of the integrated circuit design, each with a timing violation and defined at least in part by one or more of the determined number of cell instances;
• generate logic state toggle vectors by propagating logic states through the first number of circuit timing paths and the second number of circuit timing paths;
• and
• perform voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.

A computer readable storage medium having instructions stored thereon which, when executed by a computer, cause the computer to execute a method, the method comprising:

• identifying a number of cell instances with largest individual power consumption values amongst a plurality of cell instances of an integrated circuit design;
• identifying, from static timing analysis on the integrated circuit design, a first number of circuit timing paths of the integrated circuit design with largest timing violations, the integrated circuit design having a plurality of circuit timing paths formed by the plurality of cell instances;
• identifying, from the static timing analysis on the integrated circuit design, a second number of circuit timing paths of the integrated circuit design, each with a timing violation and formed at least in part by one or more of the identified number of cell instances;
• generating logic state vectors by propagating logic states through the first number of circuit timing paths and the second number of circuit timing paths;
• and
• performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.