Method and apparatus for speeding up gate-level simulation

A system comprising:

• a memory storing computer-executable instructions;
• and
• one or more hardware processors coupled to the memory and configured to:
• provide a register transfer level (RTL) description of a circuit design;
• provide a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist;
• provide one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design;
• capture a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time during which at least one operation phase of the circuit design is completed, wherein the specified period of time is less than a time period required to compete a full-scale simulation during which all operation phases of the circuit design are completed
• map the captured internal operation values to corresponding gate-level nodes of the gate-level netlist;
• capture a plurality of I/O values from the I/O variables at the beginning time of the specified period of time;
• and
• simulate the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values.

A method for performing a simulation on a circuit design, comprising:

• providing a register transfer level (RTL) description of the circuit design;
• providing a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist;
• providing one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design;
• capturing a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time during which at least one operation phase of the circuit design is completed, wherein the specified period of time is less than a time period required to compete a full-scale simulation during which all operation phases of the circuit design are completed
• mapping the captured internal operation values to corresponding gate-level nodes of the gate-level netlist based on the RTL-to-gate-level mapping details;
• capturing a plurality of I/O values from the I/O variables at the beginning time of the specified period of time;
• simulating the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values to generate a value change dump file based on the gate-level simulation of the circuit design, wherein the value change dump file includes toggling information of each gate-level node of the gate-level netlist;
• and
• estimating power consumption of the circuit design based on the value change dump file.