Method and system for functional safety verification
AssigneeCadence Design Systems, Inc.
InventorsShai Mizrachi, Eyal Gvili
Life of this patent
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Abstract
A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.
Claims17
A method for functional safety verification for use in a verification of a design under test (DUT), the method comprising:
- obtaining a set of verification tests previously executed on the DUT and related execution data;
- injecting a fault into each of the tests of the set of verification tests;
- analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree;
- and
- for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located, wherein the performing of the test ordering comprises ranking based on toggle coverage.
A non-transitory computer readable storage medium for functional safety verification for use in a verification of a design under test (DUT), having stored thereon instructions that when executed by a processor will cause the processor to:
- obtain a set of verification tests previously executed on the DUT and related execution data;
- inject a fault into each of the tests of the set of verification tests;
- obtain a user-defined percentage of faults of all of the injected faults in the design that constitutes a fault cluster;
- analyze a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree;
- and
- for each of the clusters of faults, based on the execution data, perform test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.
A system for functional safety verification for use in a verification of a design under test (DUT), the system comprising:
- a memory and
- a processor configured to:
- obtain a set of verification tests previously executed on the DUT and related execution data;
- inject a fault into each of the tests of the set of verification tests;
- analyze a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree;
- and
- for each of the clusters of faults, based on the execution data, perform test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located, wherein the performing of the test ordering comprises ranking based on toggle coverage.
Dependencies are inferred from the claim text.