Accelerator for matrix decomposition
AssigneeIntel Corporation
InventorsGurpreet Singh Kalsi, Om Ji Omer, Santhosh Kumar Rethinagiri, Anish N K, Dipan Kumar Mandal
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Abstract
Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits matrix decomposition operations into parallel operation circuits and serial operation circuits, and joins the parallel and serial operation circuits using specific dependency handling logic for efficient parallel execution. This provides fast matrix decomposition with low power consumption, reduced memory footprint, and reduced memory bandwidth.
Claims21
A hardware accelerated system comprising:
- a parallel compute circuit including a first multiply and accumulate (MAC) circuit to obtain a parallel computing input and calculate a parallel MAC single matrix column output based on the parallel computing input and a first matrix column input;
- a computation separation circuit to provide a serial computing input based on the parallel MAC single matrix column output;
- a serial compute circuit to obtain the serial computing input and calculate a serial computation output;
- a decomposition control circuit to calculate a matrix decomposition control;
- and
- a memory access control circuit to calculate the parallel computing input based on the matrix decomposition control.
A method comprising:
- obtaining a parallel computing input at a parallel compute circuit;
- calculating a parallel MAC single matrix column output at a first multiply and accumulate (MAC) circuit within the parallel compute circuit, wherein the parallel MAC single matrix column output is calculated based on the parallel computing input and a first matrix column input;
- invoking a computation separation circuit to provide a serial computing input to a serial compute circuit based on the parallel MAC single matrix column output;
- providing a serial computation output calculated by the serial compute circuit based on the serial computing input to a memory access control circuit;
- calculating a matrix decomposition control at a decomposition control circuit;
- and
- calculating the parallel computing input at the memory access control circuit based on the matrix decomposition control.
Dependencies are inferred from the claim text.