US 10,540,314 B2 · System transparent retimer

Abstract

A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operational state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward data it receives in both downstream and upstream directions of the link without frequency alteration.

Claims20

Dependent claims

A method of transferring data between interconnected devices, comprising:

at a retimer circuit configured to couple a host and a device electrically:
monitoring first data and second data received from the host and the device, respectively, the host and the device being electrically coupled to each other via an interconnect;
obtaining a host side band detection signal indicating a first data speed of the first data;
obtaining a device side band detection signal indicating a second data speed of the second data;
and
determining an operational state of the retimer based on (1) at least one of the monitored first data and the monitored second data and (2) at least one of the host side band detection signal and the device side band detection signal.

3 more elements

A retimer circuit for transferring data between interconnected devices, comprising:

a host receiver circuit configured to receive first data from a host and transmit the first data to a device via a device transmitter circuit, the host and the device being electrically coupled to each other via an interconnect;
a host transmitter circuit configured to receive second data from the device via a device receiver circuit and transmit the second data to the host;
and
a controller coupled to the host receiver circuit, the device transmitter circuit, the device receiver circuit, and the host transmitter circuit, the controller being configured to:
obtain a host side band detection signal indicating a first data speed of the first data;
obtain a device side band detection signal indicating a second data speed of the second data;
and
determine an operational state of the retimer based on (1) at least one of the monitored first data and the monitored second data and (2) at least one of the host side band detection signal and the device side band detection signal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/265,845Filed 1 Feb 2019 · continuation

Priority

17 Jul 2015

Published

US 2019/0171607 A16 Jun 2019

Granted

21 Jan 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 13/4221
On a parallel bus: being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
G06F 11/3027
Monitoring arrangements specially adapted to the computing system or computing system component being monitored: where the computing system…
G06F 11/3051
Monitoring: monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring…
Y02D 10/00
Energy efficient computing

Family

Application14/802,957Parent of this division · filed 17 Jul 2015

Application15/686,116Parent of this continuation · filed 24 Aug 2017

US 9,858,234 B2Parent of this division · filed 2 Jan 2018

US 2019/0171607 A1Pre-grant publication · published 6 Jun 2019

US 10,198,393 B2Parent of this continuation

Application15/686,116Parent of this division

US 2017/0017604 A1Published application

US 2017/0351635 A1Published application

US 10,540,314 B2This patent

From the US filing history. Foreign family members aren’t listed.

System transparent retimer

Life of this patent

System transparent retimer

Life of this patent

Abstract

Claims20