US 10,540,280 B2 · High-speed selective cache invalidates and write-backs on GPUS

Abstract

Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.

Claims20

Dependent claims

A method for performing cache operations, the method comprising:

receiving a first request to perform a first set of cache operations, the cache operations including cache invalidation operations for a first set of virtual addresses referring to a first set of data stored in a set of caches in an accelerated processing device (“APD”);
responsive to the first request, invalidating a first set of translation entries in a set of virtual-to-physical address translation caches, the first set of translation entries corresponding to the first set of virtual addresses;
determining that the first request specifies that the first set of cache operations be performed on a physically tagged cache;
translating a virtual address in the first set of virtual addresses by performing a lookup with one or more of the first set of virtual addresses, on one or more of the invalidated translation entries in the set of virtual-to-physical address translation caches and receiving one or more physical addresses from the invalidated translation entries;
and
issuing one or more transactions specified by the first request to the physically tagged cache based on the one or more physical addresses.

3 more elements

An accelerated processing device (“APD”) for performing cache operations, the APD comprising:

a high-speed invalidation unit;
a set of caches;
and
a set of virtual-to-physical address translation caches configured to store virtual-to-physical address translations,
wherein the high-speed invalidation unit is configured to:
receive a first request to perform a first set of cache operations, the cache operations including cache invalidation operations for a first set of virtual addresses referring to a first set of data stored in the set of caches;
responsive to the first request, invalidate a first set of translation entries in the set of virtual-to-physical address translation caches, the first set of translation entries corresponding to the first set of virtual addresses;
determine that the first request specifies that the first set of cache operations be performed on a physically tagged cache;
translate a virtual address in the first set of virtual addresses by performing a lookup with one or more of the first set of virtual addresses, on one or more of the invalidated translation entries in the set of virtual-to-physical address translation caches and receiving one or more physical addresses from the invalidated translation entries;
and
issue one or more transactions specified by the first request to the physically tagged cache based on the one or more physical addresses.

8 more elements

Dependencies are inferred from the claim text.

High-speed selective cache invalidates and write-backs on GPUS

Life of this patent

High-speed selective cache invalidates and write-backs on GPUS

Life of this patent

Abstract

Claims20