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US 10,540,278 B2Granted
Memory system and method of controlling cache memory
AssigneeToshiba Memory Corporation
InventorNaoya Fukuchi
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.
Claims19
A memory system comprising:
- a memory comprising a cache memory;
- and
- a controller circuit configured to:
- receive a read command from a host,
- select one of a first mode or a second mode for processing of the received read command,
- switch from the first mode to the second mode when a number of times that a plurality of the read commands that are sequentially received reaches a first number,
- switch from the second mode to the first mode when a command other than the read command is received from the host, and
- inhibit switching from the first mode to the second mode when the number of times that the switching from the first mode to the second mode reaches a second number;
- the first mode being a cache valid mode for processing of reading data associated with the received read command with using the cache memory,
- the second mode being a cache invalid mode for processing of reading data associated with the received read command without using the cache memory.
7 more elements
A memory system comprising:
- a first memory comprising a cache memory;
- a second memory that stores data;
- and
- a controller circuit configured to:
- receive a read command from a host,
- read data associated with the received read command from the second memory by processing without using the cache memory, after a number of times that a plurality of the read commands that are sequentially received reaches a first number,
- read data associated with the received read command from the first memory or the second memory by processing with using the cache memory after a command other than the read command is received from the host, and
- read data associated with the received read command from the first memory or the second memory by processing with using the cache memory after a number of times that switching from the processing with using the cache memory to the processing without using the cache memory reaches a second number.
5 more elements
A method of controlling a memory system that comprises a cache memory, the method comprising:
- receiving a read command from a host;
- selecting one of a first mode or a second mode for processing of the received read command;
- switching from the first mode to the second mode when a number of times that a plurality of the read commands that are sequentially received reaches a first number;
- switching from the second mode to the first mode when a command other than the read command is received from the host;
- and
- inhibiting switching from the first mode to the second mode when the number of times that the switching from the first mode to the second mode reaches a second number;
- the first mode being a cache valid mode for processing of reading data associated with the received read command with using the cache memory,
- the second mode being a cache invalid mode for processing of reading data associated with the received read command without using the cache memory.
5 more elements
Dependencies are inferred from the claim text.