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US 10,540,260 B2Granted
Dynamic instruction latency management in SIMD machines
AssigneeIntel Corporation
InventorsTravis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke
Life of this patent
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Abstract
In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.
Claims9
An apparatus comprising:
- a general purpose graphic processor, comprising:
- an instruction cache to receive a stream of instructions generated by a graphics program;
- an instruction unit to execute the stream of instructions;
- a general-purpose graphics processing compute block comprising a plurality of graphics compute units;
- a plurality of registers coupled to the plurality of graphics processing compute units;
- a hardware unit to selectively enable the instruction unit to execute the stream of instructions out of order;
- and
- a processor communicatively coupled to the general purpose graphics processor to:
- select a first hardware thread count to be applied to the plurality of graphics compute units to execute the stream of instructions;
- analyze the graphics program to be executed on the general purpose graphics processor at compile time to determine a set of latency parameters associated with the execution of the stream of instructions at the first hardware thread count;
- select a latency management technique to be implemented by the general purpose graphics processor based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program;
- determine the set of latency parameters associated with instruction sets implemented to execute the program at a current hardware thread count;
- determine a composite latency score for the program from the set of latency parameters at the current thread count;
- and
- compare the composite latency score at the current hardware thread count to a threshold.
12 more elements
An electronic device, comprising:
- a computer readable memory:
- a graphics processor comprising;
- an instruction cache to receive a stream of instructions generated by a graphics program;
- an instruction unit to execute the stream of instructions;
- a general-purpose graphics processing compute block comprising a plurality of graphics compute units;
- a plurality of registers coupled to the plurality of graphics processing compute units;
- a hardware unit to selectively enable the instruction unit to execute the stream of instructions out of order;
- and
- a processor communicatively coupled to the general purpose graphics processor to:
- select a first hardware thread count to be applied to the plurality of graphics compute units to execute the stream of instructions;
- analyze the graphics program to be executed on the general purpose graphics processor at compile time to determine a set of latency parameters associated with the execution of the stream of instructions at the first hardware thread count;
- and
- select a latency management technique to be implemented by the general purpose graphics processor based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program:
- determine the set of latency parameters associated with instruction count;
- determine a composite latency score for the program from the set of latency parameters at the current thread count;
- and
- compare the composite latency score at the current hardware thread count to a threshold.
14 more elements
Dependencies are inferred from the claim text.