Write technique for a bus interface system

A method of operating a master bus controller and a slave bus controller coupled along a single bus line, wherein no other bus line connects the master bus controller and the slave bus controller, the method comprising:

• generating a first set of data pulses along the single bus line representing a payload segment with the master bus controller;
• decoding the first set of data pulses representing the payload segment into a decoded payload segment with the slave bus controller;
• performing a first error check on the decoded payload segment with the slave bus controller;
• and
• generating an acknowledgment signal along the single bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check with the slave bus controller.

A master bus controller comprising:

• a memory device;
• a data modulator configured to generate a first set of data pulses representing a payload segment, wherein the first set of data pulses representing the payload segment is configured to be sent over a single bus line to a slave bus controller, wherein no other bus line connects the master bus controller and the slave bus controller;
• and
• a register circuit that includes registers, wherein the registers are configured to store the payload segment and the register circuit is configured to pass the payload segment to the memory device in response to receiving an acknowledgement pulse, and wherein the acknowledgment pulse is configured to be received over the single bus line from the slave bus controller;
• wherein the memory device is configured to store the payload segment passed from the register circuit;
• and
• wherein the master bus controller and the slave bus controller are both part of a one wire bus interface system.

A slave bus controller comprising:

• a memory device;
• a data demodulator configured to:
• decode a first set of data pulses representing a payload segment into a decoded payload segment, wherein the first set of data pulses representing the payload segment is received over a single bus line from a master bus controller, wherein no other bus line connects the master bus controller and the slave bus controller;
• perform a first error check on the decoded payload segment;
• and
• provide the decoded payload segment to the memory device when the decoded payload segment passes the first error check;
• and
• an acknowledgement generator configured to generate an acknowledgment signal so that the acknowledgement signal indicates that the decoded payload segment passed the first error check, wherein the acknowledgment signal is configured to be sent over the single bus line to the master bus controller;
• wherein the memory device is configured to store the decoded payload segment from the data demodulator.