Processor system and method for monitoring processors

An avionics system for an aircraft, which comprises at least one processor system, the processor system comprising:

• at least one application processor, comprising at least one processor core and a plurality of hardware performance counters;
• and
• a monitoring processor, which is coupled to the at least one application processor by a data-transmission interface, and which comprises:
• a look-up table, in which target performance profiles of progression over time of performance events of at least one of the plurality of hardware performance counters are stored for an application which is to be executed on the at least one application processor and monitored, and
• an evaluating logic which is linked to the look-up table and is configured to record the progression over time of performance events of the at least one of the plurality of hardware performance counters during execution of the application to be monitored on the at least one application processor and to compare the progression with the target performance profiles stored in the look-up table;
• wherein the data-transmission interface is a debug interface of the application processor.

A method for monitoring an application processor, the method comprising:

• executing at least one application to be monitored on an application processor, which has at least one processor core;
• recording progression over time of performance events for the at least one application to be monitored using a plurality of hardware performance counters;
• transmitting the recorded progressions over time of performance events from the application processor to a monitoring processor via a data-transmission interface;
• and
• comparing the recorded progression over time of performance events of the at least one of the plurality of hardware performance counters during execution of the application to be monitored with target performance profiles, stored in a look-up table of the monitoring processor, of the progression over time of performance events of at least one of the plurality of hardware performance counters;
• wherein the data interface is a debug interface of the application processor.