Hardware accelerated virtual context switching

A method for enabling a physical processor to switch between multiple virtual processor contexts without issuing a hypercall, the method comprising:

• receiving an instruction indicating that the physical processor is to switch virtual processor contexts, wherein:
• the physical processor is currently operating using a first virtual processor context,
• the instruction informs the physical processor that the physical processor is to switch virtual processor contexts so that the physical processor instead operates using a second virtual processor context, and
• the instruction is implemented in an instruction set architecture (ISA) of the physical processor such that, as a result of being implemented in the ISA of the physical processor, the instruction causes native physical processor functionality of the physical processor to perform the switch between the virtual processor contexts, in response to receiving the instruction, causing the native physical processor functionality to store a current state associated with the first virtual processor context;
• while still operating using the first virtual processor context, causing the native physical processor functionality to execute the instruction to cause the physical processor to directly switch from operating using the first virtual processor context to operating using the second virtual processor context, whereby the physical processor natively manages the switch between virtual processor contexts such that a hypercall is avoided;
• and
• determining that the first virtual processor context is associated with a first virtual machine context (VMC) list and that the second virtual processor context is associated with a second VMC list, wherein the second virtual processor context is enumerated in the first VMC list but the first virtual processor context is not enumerated in the second VMC list such that the physical processor, while operating using the first virtual processor context, is permitted to switch directly to the second virtual processor context, but the physical processor, while operating using the second virtual processor context, is not permitted to switch directly to the first virtual processor context.

A computer system comprising:

• a physical processor;
• and
• one or more computer-readable hardware storage device(s) having stored thereon computer-executable instructions that are executable by the processor to perform a method for enabling the physical processor to switch between multiple virtual processor contexts without issuing a hypercall, the method comprising:
• receiving an instruction indicating that the physical processor is to switch virtual processor contexts, wherein:
• the physical processor is currently operating using a first virtual processor context,
• the instruction informs the physical processor that the physical processor is to switch virtual processor contexts so that the physical processor instead operates using a second virtual processor context, and
• the instruction is implemented in an instruction set architecture (ISA) of the physical processor such that, as a result of being implemented in the ISA of the physical processor, the instruction causes native physical processor functionality of the physical processor to perform the switch between the virtual processor contexts, in response to receiving the instruction, causing the native physical processor functionality to store a current state associated with the first virtual processor context;
• while still operating using the first virtual processor context, causing the native physical processor functionality to execute the instruction to cause the physical processor to directly switch from operating using the first virtual processor context to operating using the second virtual processor context, whereby the physical processor natively manages the switch between virtual processor contexts such that a hypercall is avoided;
• and
• determining that the first virtual processor context is associated with a first virtual machine context (VMC) list and that the second virtual processor context is associated with a second VMC list, wherein the second virtual processor context is enumerated in the first VMC list but the first virtual processor context is not enumerated in the second VMC list such that the physical processor, while operating using the first virtual processor context, is permitted to switch directly to the second virtual processor context, but the physical processor, while operating using the second virtual processor context, is not permitted to switch directly to the first virtual processor context.