Reconfigurable processors and methods for collecting computer program instruction execution statistics

A method comprising:

• providing a reconfigurable processor that executes at least one CPU instruction of a set of central processing unit (CPU) instructions;
• modifying, using the reconfigurable processor and a memory, a function of the at least one CPU instruction of the set of CPU instructions;
• identifying an executed instruction address and a destination address pair within the reconfigurable processor of the at least one CPU instruction of the set of CPU instructions based on a defined test case;
• modifying the function of the at least one CPU instruction to record the CPU instruction during execution of the defined test case;
• executing, using the reconfigurable processor, the set of CPU instructions;
• identifying, using the at least one processor and the memory, the executed instruction address and the destination address pair within the reconfigurable processor of the at least one CPU instruction of the set of CPU instructions having the modified function when the at least one CPU instruction of the set of CPU instructions having the modified function is executed during the execution of the set of CPU instructions;
• determining an instruction path based on the identified executed instruction address and the identified destination address pair;
• determining at least one CPU instruction segment based on the instruction address and destination address pair;
• identifying at least one CPU instruction node within the set of CPU instructions;
• determining whether the at least one CPU instruction segment and CPU instruction node have been executed;
• in response to determining that the at least one CPU instruction segment and CPU instruction node have been executed, storing an execution count indicating a number of times each of the at least one CPU instruction segment and CPU instruction node has been executed;
• determining whether the executed instruction address and the destination address pair within the reconfigurable processor of the at least one CPU instruction of the set of CPU instructions having the modified function that has not been executed;
• in response to determining that the executed instruction address and the destination address pair having the modified function that has not been executed, storing the instruction path, and the instruction address and the destination address pair as a next entry for execution;
• fetching the CPU instruction based on the set of CPU instructions having the modified function;
• decoding the fetched CPU instruction having the modified function;
• and
• executing the decoded CPU instruction having the modified function.