Eliminating redundant stores using a protection designator and a clear designator

A processor for redundant stores, comprising:

• a front end including hardware circuitry to decode instructions from an instruction stream;
• a data cache unit including hardware circuitry to cache data for the processor;
• a binary translator including hardware circuitry to:
• identify a first region of the instruction stream, the first region including a first redundant store;
• mark a first starting instruction of the first region with a protection designator;
• mark a first ending instruction of the first region with a clear designator;
• and
• store an amended instruction stream including the marked first starting instruction and the marked first ending instruction;
• and
• a memory execution unit (MEU) including hardware circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.