Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment

A computer system, comprising:

• one or more processors, one or more computer-readable memories and one or more computer-readable, tangible storage devices;
• and
• program instructions, stored on at least one of the one or more computer-readable, tangible storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, to perform operations comprising:
• dividing a plurality of Input/Output (I/O) enclosures into a first set of I/O enclosures and a second set of I/O enclosures;
• performing concurrent code activation for the first set of I/O enclosures by:
• sending first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored by each I/O enclosure management engine;
• activating an update image on the first set of I/O enclosures, wherein the update image contains a first image file for firmware and a second image file for a Field-Programmable Gate Array (FPGA), and wherein activating the update image updates at least one of the firmware and the FPGA;
• and
• sending second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed;
• and
• performing concurrent code activation for the second set of I/O enclosures.

A computer-implemented method, comprising:

• dividing with a processor of a computing system, a plurality of Input/Output (I/O) enclosures into a first set of I/O enclosures and a second set of I/O enclosures;
• performing, with the processor of the computing system, concurrent code activation for the first set of I/O enclosures by:
• sending, with the processor of the computing system, first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored by each I/O enclosure management engine;
• activating, with the processor of the computing system, an update image on the first set of I/O enclosures, wherein the update image contains a first image file for firmware and a second image file for a Field-Programmable Gate Array (FPGA), and wherein activating the update image updates at least one of the firmware and the FPGA;
• and
• sending, with the processor of the computing system, second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed;
• and
• performing, with the processor of the computing system, concurrent code activation for the second set of I/O enclosures.