Method of scheduling requests to banks in a flash controller
AssigneeToshiba Memory Corporation
InventorKang Seok Seo
Life of this patent
Estimating the term…
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AssigneeToshiba Memory Corporation
InventorKang Seok Seo
Estimating the term…
A memory system includes a memory controller, a first memory bank having a first I/O bus, a second memory bank having a second I/O bus, and a channel connecting the first I/O bus and the second I/O bus to the memory controller. The channel is used to transmit data between the first memory bank and the memory controller and between the second memory bank and memory controller, and is also used to transmit a command from the memory controller to the first memory bank and the second memory bank. The memory controller includes a bank command scheduler implemented in a hardware logic block. The hardware logic block includes a plurality of direct inputs and is able to determine, based on the plurality of inputs, an order in which to output commands to the first memory bank and the second memory bank over the channel; output a first command to the first memory bank; and output a second command to the second memory bank over the channel.
A memory system comprising:
A method of scheduling a distribution of commands to a first and a second memory bank, the method comprising:
A method of determining a bank scheduling order for a NAND device having a plurality of banks with a shared channel, the method comprising:
Dependencies are inferred from the claim text.