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US 10,540,104 B2Granted
Systems and methods for packing data in a scalable memory system protocol
AssigneeMicron Technology, Inc.
InventorJ. Thomas Pawlowski
Life of this patent
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Abstract
A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.
Claims8
A method, comprising:
- receiving, via a processor, a stream of bits comprising a plurality of packets;
- identifying a first binary one value in the stream of bits;
- and
- determining a transaction type of a first packet immediately following the first binary one value, wherein the transaction type is determined based on data represented in a first set of bits that immediately follows the first binary one value, and wherein the first set of bits is part of the first packet.
1 more element
Dependencies are inferred from the claim text.