Ultra-low-power design memory power reduction scheme

An apparatus, comprising:

• a memory system comprising multiple memory blocks;
• and
• one or more circuits configured to:
• operate at least one of the multiple memory blocks in an active power state;
• determine whether a memory block operating in the active power state during a current monitoring interval has been accessed or not accessed during the current monitoring interval;
• increase an age associated with the memory block in response to a determination that the memory block was not accessed in the current monitoring interval;
• determine whether the age associated with the at least one memory block has crossed a threshold that triggers a transition to a low-leakage power state;
• and
• transition the at least one memory block from the active power state to the low-leakage power state in response to the age associated with the at least one memory block crossing the threshold that triggers the transition to the low-leakage power state and one or more performance-related criteria associated with the at least one memory block permitting the transition to the low-leakage power state, wherein data stored in the at least one memory block is retained in the low-leakage power state, and wherein the transition comprises a switch of the at least one memory block from a shared voltage rail to a low power voltage rail.

An apparatus, comprising:

• means for determining whether a memory block operating in an active power state during a current monitoring interval has been accessed or not accessed during the current monitoring interval;
• means for increasing an age associated with the memory block in response to a determination that the memory block was not accessed in the current monitoring interval;
• means for determining whether the age associated with the memory block has crossed a threshold that triggers a transition to a low-leakage power state;
• and
• means for transitioning the memory block from the active power state to the low-leakage power state in response to the age associated with the memory block crossing the threshold that triggers the transition to the low-leakage power state and one or more performance-related criteria associated with the memory block permitting the transition to the low-leakage power state, wherein data stored in the memory block is retained in the low-leakage power state, and wherein the transition comprises switching the memory block from a shared voltage rail to a low power voltage rail.

A non-transitory computer-readable medium storing computer-executable instructions, the stored computer-executable instructions configured to cause one or more circuits to:

• determine whether a memory block operating in an active power state during a current monitoring interval has been accessed or not accessed during the current monitoring interval;
• increase an age associated with the memory block in response to a determination that the memory block was not accessed in the current monitoring interval;
• determine whether the age associated with the memory block has crossed a threshold that triggers a transition to a low-leakage power state;
• and
• transition the memory block from the active power state to the low-leakage power state in response to the age associated with the memory block crossing the threshold that triggers the transition to the low-leakage power state and one or more performance-related criteria associated with the memory block permitting the transition to the low-leakage power state, wherein data stored in the memory block is retained in the low-leakage power state, and wherein the transition comprises switching the memory block from a shared voltage rail to a low power voltage rail.