WiFi memory power minimization

A method comprising, under control of one or more computing devices:

• determining, via an embedded processor of a system on chip, to fetch a page from a host memory of a host system including the host memory and a host processor configured to be operated in a sleep state;
• identifying that the host processor is operating in the sleep state;
• and
• in response to identifying that the host processor is operating in the sleep state, fetching the page from the host memory into an embedded memory of the system on chip without waking the host processor from the sleep state;
• wherein fetching the page comprises transitioning a communications bus from a low power state to a full power state, and operating the communications bus to transfer the page from the host memory into the embedded memory.

A system on chip comprising:

• a computer-readable memory storing instructions to control operations of the system;
• an embedded processor configured by the instructions in the computer-readable memory;
• and
• an embedded memory configured for storing one or both of code and data usable during the operations of the system, the embedded memory including a resident memory portion and a pageable memory portion;
• wherein the instructions configure the embedded processor to:
• transfer, via a communications bus, a page between the pageable memory portion and a secondary memory of a host system outside of the system on chip without waking a host processor associated with the secondary memory;
• operate the communications bus in at least a full power state and a lower power state;
• and
• transition the communications bus between the lower power state and the full power state by sending a clock request signal to an additional processor of the host system that consumes less power during operations than the host processor, wherein the additional processor is configured to act as a proxy bus master without waking the host processor when the host processor is being operated in the sleep state.

A device comprising:

• a host system including a host processor configured to be operated in a sleep state and a host memory;
• a system on chip including:
• a computer-readable memory storing instructions to control operations of the system on chip,
• an embedded processor configured by the instructions m the computer-readable memory, and
• an embedded memory configured for storing pages usable during the operations of the system on chip;
• and
• a communications channel configured to provide data communications between at least the embedded memory of the system on chip and the host memory;
• wherein the instructions configure the embedded processor to transfer a page between the embedded memory and the host memory without waking the host processor from the sleep state, and to operate the communications bus in at least a full power state and a lower power state.