Memory device alert of completion of internally self-timed power-up and reset operations
AssigneeAdesto Technologies Corporation
InventorsBard M. Pedersen, Paul Hill
Life of this patent
Estimating the term…
Abstract
A memory device can include: a non-volatile storage register configured to store an active reset polling enable bit that corresponds to a reset operation; a controller configured to control execution of the reset operation on the memory device; an operation completion indicator configured to provide a reset recovery indication external to the memory device when the reset operation has completed and the active reset polling enable bit is set; and a command decoder configured to receive a command to be executed on the memory device in response to the reset recovery indication.
Claims20
A memory device, comprising:
- a) a non-volatile storage register configured to store an active reset polling enable bit that corresponds to a reset operation;
- b) a reset control circuit coupled to the non-volatile storage register, and being configured to control execution of the reset operation on the memory device;
- c) an output circuit configured to transition a signal on an output pin from a high impedance state to a first low impedance state in response to the reset operation being initiated on the memory device and the active reset polling enable bit being set;
- d) an operation completion indicator configured to automatically output a reset recovery indication from the memory device when the reset operation has completed and the active reset polling enable bit is set, wherein the reset recovery indication comprises a transition of the signal on the output pin from the first low impedance state to a second low impedance state;
- e) a command decoder configured to receive a command to be executed on the memory device in response to the reset recovery indication;
- and
- f) a status register configured to be written to along with the reset recovery indication to indicate that the reset operation has completed execution on the memory device, wherein the status register is also configured to store the active reset polling enable bit.
A method of controlling a memory device, the method comprising:
- a) storing, in a non-volatile storage register, an active reset polling enable bit that corresponds to a reset operation;
- b) controlling execution of the reset operation on the memory device;
- c) transitioning, by an output circuit, a signal on an output pin from a high impedance state to a first low impedance state in response to the reset operation being initiated on the memory device and the active reset polling enable bit being set;
- d) determining when the reset operation has completed on the memory device;
- e) automatically outputting a reset recovery indication from the memory device when the reset operation has completed and the active reset polling enable bit is set, wherein the reset recovery indication comprises a transition of the signal on the output pin from the first low impedance state to a second low impedance state;
- f) receiving, by a command decoder, a command to be executed on the memory device in response to the reset recovery indication;
- and
- g) writing a status register along with the reset recovery indication to indicate that the reset operation has completed execution on the memory device, wherein the status register is also configured to store the active reset polling enable bit.
Dependencies are inferred from the claim text.