Display device having an oxide semiconductor transistor

A display device comprising:

• a first scan line over a substrate;
• a second scan line adjacent to the first scan line;
• a first insulating layer over the first scan line and the second scan line;
• an oxide semiconductor layer over the first insulating layer, wherein the oxide semiconductor layer comprises a channel formation region overlapping with the first scan line;
• a signal line over and electrically connected to the oxide semiconductor layer;
• a metal layer over the oxide semiconductor layer;
• an inorganic insulating layer over the signal line and the metal layer, wherein the inorganic insulating layer is in contact with a top surface of the oxide semiconductor layer and comprises silicon and oxygen;
• an organic insulating layer over the inorganic insulating layer;
• and
• a pixel electrode over the inorganic insulating layer, the pixel electrode being electrically connected to the oxide semiconductor layer through the metal layer,
• wherein the signal line intersects the first scan line and the second scan line,
• wherein no conductive layer is provided between the signal line and the substrate in a region between the first scan line and the second scan line,
• wherein the display device has a resolution of 60 ppi or more,
• wherein the display device is a liquid crystal display device,
• wherein frequency of rewriting a data signal in a pixel is able to be higher than 60 Hz, the pixel comprising the pixel electrode,
• wherein the first scan line has a stacked structure comprising a first layer comprising titanium, tantalum or molybdenum and a second layer comprising copper or tungsten,
• wherein the first insulating layer has a stacked structure comprising a third layer comprising silicon and nitrogen, and a fourth layer comprising silicon and oxygen over the third layer,
• wherein the metal layer has a stacked structure comprising a fifth layer comprising aluminum or copper and a sixth layer comprising titanium or molybdenum, and
• wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

A display device comprising:

• a scan line;
• an oxide semiconductor layer over the scan line through a first insulating layer, the oxide semiconductor layer overlapping with the scan line;
• a signal line over and electrically connected to the oxide semiconductor layer;
• an inorganic insulating layer over the signal line;
• and
• a pixel electrode electrically connected to the oxide semiconductor layer,
• wherein the display device has a resolution of 60 ppi or more,
• wherein the display device is a liquid crystal display device,
• wherein frequency of rewriting a data signal in a pixel is changeable and is able to be higher than 60 Hz, the pixel comprising the pixel electrode,
• wherein the first insulating layer has a stacked structure comprising a first layer comprising silicon and nitrogen, and a second layer comprising silicon and oxygen over the first layer,
• wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and
• wherein off-state current of a transistor comprising the oxide semiconductor layer is smaller than or equal to 1×10−12 A in the case where drain voltage is +10 V and gate voltage is within a range of −5 V to −20 V.

A semiconductor device comprising:

• a transistor comprising an oxide semiconductor layer that comprises a channel formation region;
• and
• a pixel electrode electrically connected to the channel formation region through a metal layer of the transistor, the pixel electrode not overlapping with the channel formation region,
• wherein the pixel electrode does not overlap with a signal line electrically connected to one of a source and a drain of the transistor and does not overlap with a scan line electrically connected to a gate of the transistor,
• wherein a gate insulating layer of the transistor has a stacked structure comprising a first layer comprising silicon and nitrogen, and a second layer comprising silicon and oxygen over the first layer,
• wherein off-state current of the transistor is smaller than or equal to 1×10−12 A in the case where drain voltage is +10 V and gate voltage is within a range of −5 V to −20 V.