Scan architecture for interconnect testing in 3D integrated circuits

A device, comprising:

• a first die;
• and
• a second die stacked below the first die, at least one of the first die or second die including level shifters and interconnections between the first die and the second die, at least one of the first die or the second die having a circuit for performing a function, the circuit having a functional path,
• wherein each of the first and second dies comprise:
• a plurality of latches, including a respective latch corresponding to each one of the interconnections, and
• a plurality of multiplexers, each multiplexer connected to a respective one of the plurality of latches and a respective functional path and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die,
• wherein the plurality of latches in the first die includes a first latch without a connection to a multiplexer, and
• wherein the first latch is configured to transmit a signal to a corresponding latch in the second die by a testing connection that is used during the scan chain test.