Scan data control apparatus and electronic system having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyoung-Heon Jeong, Ho-Sung Kim, Sung-Jae Lee
Life of this patent
Estimating the term…
Abstract
A scan data control apparatus includes a trigger circuit, a scan sequencer, a shift register, and a transmitter. The trigger circuit is configured to receive a trigger signal, detect a malfunction of a system and output a scan mode start signal and a scan mode end signal. The scan sequencer is configured to output scan enable signals corresponding to a CPU and a master to the CPU and the master. The shift register is configured to receive scan data of the CPU and the master from the CPU and the master. The transmitter is configured to receive the scan data of the CPU and the master and output the scan data to a memory.
Claims19
A scan data control apparatus comprising:
- a trigger circuit configured to receive a trigger signal, detect a malfunction of a system in response to the trigger signal;
- a scan sequencer circuit configured to output, in response to the trigger circuit detecting the malfunction, scan enable signals corresponding to a central processing unit (CPU) and a master device to the CPU and the master device, respectively;
- a shift register configured to receive, in response to a scan clock signal received from the scan sequencer circuit, scan data of the CPU and the master device from the CPU and the master device, respectively;
- and
- a transmitter circuit configured to receive, from the shift register, the scan data of the CPU and the master device and output the scan data for storage within a memory, wherein
- the trigger circuit outputs a scan mode end signal in response to the storage of the scan data within the memory being completed.
An electronic system comprising:
- a bus configured to transmit data;
- a memory configured to store the data;
- a central processing unit (CPU) and a master device which are connected to the bus;
- a power management circuit connected to the bus and configured to provide power to the CPU and the master device;
- a memory interface connected to the bus and configured to control an operation of the memory;
- and
- a scan data control circuit configured to detect a malfunction of a system and store scan data of the CPU and the master device within the memory, wherein the scan data control circuit comprises:
- a trigger circuit configured to detect the malfunction of the system;
- a scan sequencer circuit configured to output, in response to the trigger circuit detecting the malfunction, scan enable signals corresponding to the CPU and the master device to the CPU and the master device, respectively;
- a shift register configured to receive the scan data of the CPU and the master device from the CPU and the master device, respectively;
- and
- a transmitter circuit configured to receive the scan data of the CPU and the master device from the shift register and output the scan data to the memory, wherein
- the trigger circuit outputs a scan mode end signal in response to storage of the scan data within the memory being completed.
A system on chip comprising:
- a scan control circuit that detects a system malfunction and communicates a scan mode start signal in response to detecting the system malfunction;
- a power management circuit that communicates a scan request signal to a processor in response to receiving the scan mode start signal from the scan control circuit;
- and
- the processor that communicates, in response to a scan enable signal received from the scan control circuit, scan data to the scan control circuit for storage in a memory device.
Dependencies are inferred from the claim text.