Through process flow intra-chip and inter-chip electrical analysis and process control using in-line nanoprobing
AssigneeFEI EFA, Inc.
InventorsVladimir Ukraintsev, Israel Niv, Ronen Benzion
Life of this patent
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Abstract
System for performing in-line nanoprobing on semiconductor wafer. A wafer support or vertical wafer positioner is attached to a wafer stage. An SEM column, an optical microscope and a plurality of nanoprobe positioners are all attached to the ceiling. The nanoprobe positioners have one nanoprobe configured for physically contacting selected points on the wafer. A force (or touch) sensor measures contact force applied by the probe to the wafer (or the moment) when the probe physically contacts the wafer. A plurality of drift sensors are provided for calculating probe vs. wafer alignment drift in real-time during measurements.
Claims23
A system for performing in-line nanoprobing on a semiconductor wafer, comprising:
- a vacuum chamber having a floor, a sidewall, and a ceiling;
- a navigation stage having a traveling part and a stationary part and a bearing that when activated, enables relative motion between the traveling part and the stationary part;
- a wafer support attached to the traveling part of the navigation stage;
- a scanning electron microscope (SEM) column attached to the ceiling;
- and
- a plurality of nanoprobe positioners attached to the ceiling, each nanoprobe positioner having a nanoprobe fork configured for physically contacting selected points on the wafer, each of the nanoprobe positioners being attached to the ceiling in close proximity to the SEM column so as to enable the nanoprobe positioner to insert its nanoprobe fork into a field of view of the SEM column.
A method for performing electrical testing of devices in a semiconductor wafer, comprising:
- positioning a semiconductor wafer on a stage inside a chamber;
- placing the wafer and the chamber under a vacuum;
- and without breaking the vacuum, performing the following steps:
- determining alignment of the wafer on the stage by imaging the wafer using an optical microscope;
- spatially moving the stage so as to place a region of interest (ROI) in the wafer below a column of a scanning electron microscope (SEM);
- imaging the ROI using the SEM to identify a plurality of targets within the ROI;
- identifying a subset of targets of the plurality of targets to contact;
- assigning each target of the subset of targets to one probe fork of a plurality of probe forks, wherein a subset of probe forks of a plurality of probe forks is assigned, and wherein each of the plurality of probe forks is coupled to a respective nanoprobe positioner of a plurality of nanoprobe positioners;
- generating a set of movement vectors for at least each probe fork of the subset of probe forks to move to an area above their assigned target of the subset of targets;
- operating at least an respective subset of the plurality of nanoprobe positioners so as to cause each nanoprobe positioner of the subset of nanoprobe positioners to place their respective probe forks above the assigned target of the subset of targets;
- co-registering the probe forks of the subset of probe forks and the assigned targets using pattern recognition;
- operating at least the subset the plurality of nanoprobe positioners to land each of their respective prober forks on its assigned target of the subset of targets;
- and
- performing electrical probing of the wafer.
Dependencies are inferred from the claim text.