Image sensor with tolerance optimizing interconnects
AssigneeDePuy Synthes Products, Inc.
InventorLaurent Blanquart
Life of this patent
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Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.
Claims16
An imaging sensor comprising:
- a first substrate including a pixel array disposed on a top of the first substrate and a plurality of interconnects disposed through the first substrate to a bottom of the first substrate;
- a second substrate including supporting circuitry for the pixel array, the second substrate being connected to the bottom of the first substrate by the plurality of interconnects,
- wherein the pixel array includes a plurality of pixel columns,
- wherein a read bus is provided for each one of the plurality of pixel columns on the first substrate,
- wherein each read bus on the first substrate provides electrical communication for one of the plurality of pixel columns to the supporting circuitry on the second substrate via a read bus on the second substrate, and
- wherein the interconnect further connects the read bus on the first substrate to the read bus on the second substrate.
An imaging sensor comprising:
- a first substrate including a pixel array disposed on a top of the first substrate and a plurality of interconnects disposed through the first substrate to a bottom of the first substrate,
- wherein the pixel array is arranged in a plurality of pixel columns where each column of pixels in the pixel array is M pixels wide and N pixels long;
- a second substrate including supporting circuitry for the pixel array, the second substrate being connected to the bottom of the first substrate by the plurality of interconnects,
- wherein a read bus is provided for each one of the plurality of pixel columns on the first substrate,
- wherein each read bus on the first substrate provides electrical communication for one of the plurality of pixel columns to the supporting circuitry on the second substrate via a read bus on the second substrate, and
- wherein the interconnect further connects the read bus on the first substrate to the read bus on the second substrate.
Dependencies are inferred from the claim text.