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US 10,536,178 B2Granted
High speed receivers circuits and methods
AssigneeIntel Corporation
InventorsKevin Chang, Stefano Giaconi
Life of this patent
Estimating the term…
Abstract
The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.
Claims20
An apparatus comprising:
- a termination impedance;
- a base line wander corrector (BLWC) coupled to the termination impedance;
- and
- a VGA coupled to the BLWC, the VGA comprising:
- an amplifier;
- and
- a negative impedance circuit coupled to the amplifier.
4 more elements
An apparatus comprising:
- means for amplifying a differential signal;
- means for cancelling offset associated with the means for amplifying;
- and
- means for reducing parasitic capacitance of one or more nodes of the means for amplifying.
1 more element
An apparatus comprising:
- a first integrated circuit (IC) having a transmitter to send a bit stream;
- a transmission media;
- and
- a second IC coupled to the first IC via the transmission media, wherein the second IC includes a receiver which is to receive the bit stream, and wherein the receiver comprises:
- a termination impedance;
- a base line wander corrector (BLWC) coupled to the termination impedance;
- and
- a VGA coupled to the BLWC, the VGA comprising:
- an amplifier;
- and
- a negative impedance circuit coupled to the amplifier.
8 more elements
Dependencies are inferred from the claim text.