Programmable bit alignment at serial-to-parallel stage of SerDes
AssigneeQUALCOMM Incorporated
InventorsAnand Gaurav, Bo Sun
Life of this patent
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Abstract
In certain aspects, a serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages includes one or more demultiplexers. The serial-to-parallel converter also includes demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages, and a pattern detector coupled to the demultiplexer control circuits.
Claims21
A serial-to-parallel converter, comprising:
- multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages comprises one or more demultiplexers;
- demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages;
- and
- a pattern detector coupled to the demultiplexer control circuits, wherein the pattern detector is configured to
- detect a pattern in the serial data stream;
- and
- upon detecting the pattern, output a pattern detection signal to the demultiplexer control circuits.
A serial-to-parallel converter, comprising:
- a demultiplexer configured to receive a serial data stream and split the serial data stream into first and second parallel data signals;
- a demultiplexer control circuit coupled to the demultiplexer;
- and
- a pattern detector coupled to the demultiplexer control circuit, wherein the pattern detector is configured to:
- detect a pattern in the serial data stream;
- and
- upon detecting the pattern, output a pattern detection signal to the demultiplexer control circuit.
A method for operating a serial-to-parallel converter, wherein the serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, and each of the stages comprises one or more demultiplexers, the method comprising:
- detecting a pattern in the serial data stream;
- and
- for each of the stages, outputting a respective clock signal to the one or more demultiplexers of the stage upon detecting the pattern.
Dependencies are inferred from the claim text.