US 10,535,114 B2 · Controlling multi-pass rendering sequences in a cache tiling architecture

Abstract

In one embodiment of the present invention a driver configures a graphics pipeline implemented in a cache tiling architecture to perform dynamically-defined multi-pass rendering sequences. In operation, based on sequence-specific configuration data, the driver determines an optimized tile size and, for each pixel in each pass, the set of pixels in each previous pass that influence the processing of the pixel. The driver then configures the graphics pipeline to perform per-tile rendering operations in a region that is translated by a pass-specific offset backward—vertically and/or horizontally—along a tiled caching traversal line. Notably, the offset ensures that the required pixel data from previous passes is available. The driver further configures the graphics pipeline to store the rendered data in cache lines. Advantageously, the disclosed approach exploits the efficiencies inherent in cache tiling architecture while honoring highly configurable data dependencies between passes in multi-pass rendering sequences.

Claims20

Dependent claims

A computer-implemented method for performing a multi-pass rendering sequence in a tile-based architecture, the method comprising:

calculating a tile size for a current pass through a graphics processing pipeline based at least on algorithmic dependencies between the current pass and one or more previous passes through the graphics processing pipeline, wherein a given generation region is processed by the graphics processing pipeline in each pass;
calculating a set of first generation offsets for the current pass based on a first subset of the algorithmic dependencies;
determining a first generation region for the current pass based on the tile size and the set of first generation offsets;
and
processing the first generation region for the current pass by:
configuring the graphics processing pipeline to generate first graphics data for a first set of pixels included in the first generation region, and
configuring the graphics processing pipeline to store the first graphics data in a first set of cache lines included in a cache memory.

4 more elements

One or more non-transitory, computer-readable storage media including instructions that, when executed by one or more processors, cause the one or more processors to perform a multi-pass rendering sequence in a tile-based architecture, by performing the steps of:

calculating a tile size for a current pass through a graphics processing pipeline based at least on algorithmic dependencies between the current pass and one or more previous passes through the graphics processing pipeline, wherein a given generation region is processed by the graphics processing pipeline in each pass;
calculating a set of first generation offsets for the current pass based on a first subset of the algorithmic dependencies;
determining a first generation region for the current pass based on the tile size and the set of first generation offsets;
and
processing the first generation region for the current pass by:
configuring the graphics processing pipeline to generate first graphics data for a first set of pixels included in the first generation region, and
configuring the graphics processing pipeline to store the first graphics data in a first set of cache lines included in a cache memory.

4 more elements

A system configured to perform a multi-pass rendering sequence, the system comprising:

a graphics processing pipeline that implements a tile-based architecture;
and
a device driver coupled to the graphics processing pipeline that:
calculates a tile size for a current pass through the graphics processing pipeline based at least on algorithmic dependencies between the current pass and one or more previous passes through the graphics processing pipeline, wherein a given generation region is processed by the graphics processing pipeline in each pass,
calculates a set of first generation offsets for the current pass based on a first subset of the algorithmic dependencies,
determines a first generation region for the current pass based on the tile size and the set of first generation offsets, and
processes the first generation region for the current pass by:
configuring the graphics processing pipeline to generate first graphics data for a first set of pixels included in the first generation region, and
configuring the graphics processing pipeline to store the first graphics data in a first set of cache lines included in a cache memory.

6 more elements

Dependencies are inferred from the claim text.

Controlling multi-pass rendering sequences in a cache tiling architecture

Life of this patent

Controlling multi-pass rendering sequences in a cache tiling architecture

Life of this patent

Abstract

Claims20