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US 10,530,372 B1Granted
Systems and methods for digital synthesis of output signals using resonators
AssigneeMY Tech, LLC
InventorsTommy Yu, Avanindra Madisetti
Life of this patent
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Abstract
Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
Claims27
A direct frequency synthesizer comprising:
- a high speed resonator that generates a frequency signal;
- an oscillator that receives the frequency signal and generates an output signal;
- a clock generator that receives the output signal of the oscillator and generates a clock signal from the output signal;
- a controller that generates a frequency control word describing a desired output digital signal;
- and
- a direct digital frequency synthesizer that receives the clock signal and the frequency control word and generates a desired digital output signal based on the clock signal and frequency control word;
- and
- a high speed digital to analog converter that receives the output signal from the oscillator and the desired digital output signal from the direct digital frequency synthesizer and outputs an analog signal based on the desired digital output signal.
5 more elements
A method for generating a signal from a high speed resonator comprising:
- generating a frequency signal using a high speed resonator
- receiving the frequency signal in an oscillator;
- generating an output signal from the frequency signal using the oscillator;
- receiving the output signal of the oscillator in a clock generator;
- generating a clock signal from the output signal of the oscillator using the clock generator;
- generating a frequency control word describing a desired output digital signal using a controller;
- receiving the clock signal and the frequency control word in a direct digital frequency synthesizer;
- and
- generating a desired digital output signal based on the clock signal and frequency control word using the direct digital frequency synthesizer;
- receiving the output signal from the oscillator and the desired digital output signal from the direct digital frequency synthesizer in a high speed digital to analog converter;
- and
- converting the desired digital output signal to an analog output signal.
9 more elements
A phase lock loop that receives a reference signal,
- outputs a high frequency clock signal and feeds back an error correction signal for adding to the reference signal, the phase lock loop comprising:
- a high frequency oscillator that receives a high frequency signal and generates a reference clock signal;
- a low frequency oscillator that receives the low frequency signal and generates a stable clock signal;
- a frequency ratio estimator that determines a ratio between the reference clock signal and the stable clock signal;
- and
- a fractional N divider that receives a signal indicating the ratio between the reference clock signal and stable clock signal and an output signal of the PLL and generates an error feedback correction based upon the ratio of the reference clock signal to the stable clock signal;
- and
- a crystal resonator that generates a low frequency signal and provides the low frequency signal to the low frequency oscillator.
5 more elements
The phase lock loop of 17 further comprising:
- a delta sigma modulator that receives the output from the frequency ratio estimator and generates a control signal for the fractional N divider.
A method for generating a high frequency clock signal comprising:
- generating a reference signal using a high frequency oscillator;
- generating a stable signal using a low frequency oscillator;
- receiving the reference clock signal and an error correction signal in a phase detector;
- generating a corrected reference clock signal from the reference clock signal and the error correction signal using the phase detector;
- receiving the corrected reference clock signal in a loop filter;
- generating a voltage control signal from the corrected reference clock signal using the loop filter;
- receiving the voltage control signal in a voltage control oscillator;
- generating a high frequency clock signal from the voltage control signal using the voltage controlled oscillator;
- determining a ratio between the reference signal and the stable signal using a frequency ratio estimator;
- and
- controlling a fractional N divider using the ratio between the reference signal and the stable signal to generate the corrected error signal from the high frequency clock signal generated by the voltage controlled oscillator.
8 more elements
Dependencies are inferred from the claim text.