Column line clamp circuit for imaging array
AssigneeFoveon, Inc.
InventorsSudipta Saha, Shivani Gupta
Life of this patent
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Abstract
In an imaging array having a plurality of pixel sensors arranged in a plurality of rows and columns, pixel data being read out on column lines of the array, a column line voltage clamp circuit for column lines of the array includes a master voltage clamp circuit coupled to provide a reference voltage clamp level on a reference node, and a slave voltage clamp circuit coupled to each column line in the imaging array, each slave voltage clamp circuit configured to clamp voltage on the column line to a column voltage clamp level derived from the reference voltage level.
Claims14
In an imaging array having a plurality of pixel sensors arranged in a plurality of rows and columns, pixel data being read out on column lines of the array, a column line voltage clamp circuit for column lines of the array comprising:
- a master voltage clamp circuit coupled to provide a fixed reference maximum brightness voltage clamp level on a reference node;
- a slave maximum brightness voltage clamp circuit coupled to each column line in the imaging array, each slave voltage clamp circuit configured to clamp voltage on the column line to a fixed column voltage clamp level derived from the fixed reference voltage level;
- and
- wherein the reference voltage maximum brightness clamp level is established by a reference source-follower transistor driving a reference current source load, a gate of the reference source-follower transistor driven by an operational amplifier having a non-inverting input coupled to a reference voltage potential, and an inverting input coupled to the reference node, and the slave voltage clamp circuit coupled to each column line comprises a column source-follower transistor driving a column current source load connected to the column line, the column current source load sourcing a current derived from the reference current source load.
In an imaging array having a plurality of pixel sensors arranged in a plurality of rows and columns, pixel data being read out on column lines of the array, a column line voltage clamp circuit for column lines of the array comprising:
- a master voltage maximum brightness clamp circuit coupled to provide a fixed reference voltage clamp level on a reference node;
- a slave voltage maximum brightness clamp circuit coupled to each column line in the imaging array, each slave maximum brightness voltage clamp circuit configured to clamp voltage on the column line to a fixed column maximum brightness voltage clamp level derived from the fixed reference voltage level during pixel data readout to define the lowest voltage to which columns are allowed to drop;
- and
- wherein the reference maximum brightness voltage clamp level is established by a reference source-follower transistor driving a reference current source load, a gate of the reference source-follower transistor driven by an operational amplifier having a non-inverting input coupled to a reference voltage potential, and an inverting input coupled to the reference node, and the slave maximum brightness voltage clamp circuit coupled to each column line comprises a column source-follower transistor driving a column current source load connected to the column line, the column current source load sourcing a current derived from the reference current source load.
Dependencies are inferred from the claim text.