Clock distribution system
AssigneeNorthrop Grumman Systems Corporation
InventorsJoshua A. Strong, Anna Y. Herr, Quentin P. Herr, Steven B. Shauck
Life of this patent
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Abstract
One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.
Claims19
A clock distribution system comprising:
- a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal, the standing-wave resonator comprising at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal;
- and
- at least one clock line inductively coupled to each of the at least one anti-node portion of the standing-wave resonator and to at least one conductor of an associated circuit, the at least one clock line being configured to inductively provide the sinusoidal clock signal for timing functions associated with the associated circuit.
A clock distribution system comprising:
- a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal, the standing-wave resonator comprising at least one anti-node portion associated with a predetermined length of the standing-wave resonator defined by a current amplitude of the sinusoidal clock signal that is between a predetermined current amplitude threshold associated with the sinusoidal clock signal and a peak current amplitude of the sinusoidal clock signal associated with an absolute anti-node;
- and
- a plurality of clock lines that are each inductively coupled to an associated circuit and to one of the at least one anti-node portion at a predetermined inductance magnitude based on a distance from the absolute anti-node along a length of the respective one of the at least one anti-node portion to provide a substantially equal current amplitude in each of the plurality of clock lines, the plurality of clock lines being configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.
An integrated circuit (IC) chip comprising:
- a reciprocal quantum logic (RQL) circuit configured to operate based on an in-phase sinusoidal clock signal and a quadrature-phase sinusoidal clock signal;
- a first standing-wave resonator configured to receive and to resonate the in-phase sinusoidal clock signal;
- a second standing-wave resonator configured to receive and to resonate the quadrature-phase sinusoidal clock signal, the first and second standing-wave resonators each comprising at least one anti-node portion associated with a peak current amplitude of the respective in-phase and quadrature-phase sinusoidal clock signals;
- and
- at least one clock line inductively coupled to the RQL circuit and inductively coupled to each of the at least one anti-node portion of each of the first and second standing-wave resonators, the at least one clock line being configured to propagate a respective one of the in-phase and quadrature-phase sinusoidal clock signals for timing functions associated with the RQL circuit.
Dependencies are inferred from the claim text.