Reference voltage generator

A reference voltage generator comprising:

• a differential amplification circuit including a positive input terminal coupled to a supply voltage to receive a voltage from the supply voltage and a negative input terminal coupled to an output terminal of the differential amplification circuit, the differential amplification circuit structured to perform a reset operation based on the received voltage from the supply voltage during a reset period and amplify a difference between a first initial voltage applied to the positive input terminal and a second initial voltage applied to the negative input terminal during a reference voltage generation period;
• and
• first and second voltage storage circuits coupled to the positive input terminal and the negative input terminal, respectively, and structured to store the first initial voltage and the second initial voltage, respectively,
• wherein the second voltage storage circuit comprises:
• a capacitor coupled between the negative input terminal of the differential amplification circuit and a second node located between the negative input terminal and a ground voltage;
• and
• a switch turned on in the reset period to couple the second node to the ground voltage, and wherein the second voltage storage circuit comprises:
• a first resistor coupled between the output terminal of the differential amplification circuit and the second node;
• a second resistor coupled between the second node and an first terminal of the first transistor;
• and
• the first transistor having the first terminal coupled to the second resistor and second and third terminals that are coupled to the ground voltage.

A reference voltage generator comprising:

• a differential amplifier structured to differentially amplify a difference between a voltage applied to a positive input terminal thereof and a voltage applied to a negative input terminal thereof;
• a first switch turned on in a reset period, and coupled between an output terminal of the differential amplifier and the negative input terminal of the differential amplifier;
• a second switch turned on in a reference voltage generation period, and having one terminal coupled to the output terminal of the differential amplifier;
• a first resistor coupled between the other terminal of the second switch and a first node;
• a first PNP transistor having an emitter terminal coupled to the first node and base and collector terminals coupled to a ground voltage;
• a first capacitor coupled between the positive input terminal of the differential amplifier and the first node, and suitable for storing a differential amplifier offset-containing initial voltage applied to the positive input terminal of the differential amplifier and applying the stored voltage to the positive input terminal of the differential amplifier;
• a third switch turned on in the reset period, and coupled between the first node and the ground voltage;
• a second resistor coupled between the other terminal of the second switch and a second node;
• a third resistor having one terminal coupled to the second node;
• a second PNP transistor having an emitter terminal coupled to the other terminal of the third resistor and base and collector terminals coupled to the ground voltage;
• a second capacitor coupled between the negative input terminal of the differential amplifier and the second node, and suitable for storing the differential amplifier offset-containing initial voltage applied to the negative input terminal of the differential amplifier and applying the stored voltage to the negative input terminal of the differential amplifier;
• and
• a fourth switch turned on in the reset period and coupled between the second node and the ground voltage.