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US 10,520,901 B2Granted
Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation
AssigneeQUALCOMM Incorporated
InventorsZhengzheng Wu, Deping Huang, Jeffrey Mark Hinrichs, Marzio Pedrali-Noy
Life of this patent
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Abstract
A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.
Claims15
A time-to-digital converter for measuring the time between a first clock edge and a second clock edge, comprising:
- a slow oscillator configured to oscillate a slow oscillator output signal responsive to the first clock edge;
- a coarse counter configured to count a coarse count responsive to cycles of the slow oscillator output signal;
- a fast oscillator configured to oscillate a fast oscillator output signal responsive to the second clock edge;
- a fine counter configured to count a fine count responsive to cycles of the fast oscillator output signal, wherein a frequency for the fast oscillator output signal is greater than a frequency for the slow oscillator output signal;
- a first current source configured to sink a first current prior to the first clock edge and to not sink the first current subsequent to the first clock edge, wherein the first current is a replica of an operating current drawn by the slow oscillator;
- and
- a second current source configured to sink a second current prior to the second clock edge and to not sink the second current subsequent to the second clock edge, wherein the second current is a replica of an operating current drawn by the fast oscillator.
4 more elements
A method, comprising:
- oscillating a slow oscillator output signal responsive to a first clock edge for a first clock signal;
- oscillating a fast oscillator output signal responsive to a second clock edge following the first clock edge, wherein a frequency for the fast oscillator output signal is greater than a frequency for the slow oscillator output signal;
- counting cycles of the slow oscillator output signal to count a coarse count;
- counting cycles of the fast oscillator output signal to count a fine count;
- measuring a delay between the first clock edge and the second clock edge responsive to a function of the coarse count and the fine count to form a measurement of the delay;
- comparing the fine count to a ratio of a frequency for the fast oscillator output signal to a frequency of the slow oscillator output signal to form a tuning code;
- and
- delaying the first clock signal responsive to the tuning code.
5 more elements
Dependencies are inferred from the claim text.